diff options
Diffstat (limited to 'src/mainboard/google/rex/variants/screebo')
8 files changed, 74 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/screebo/Makefile.inc b/src/mainboard/google/rex/variants/screebo/Makefile.inc new file mode 100644 index 0000000000..6c29346470 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/rex/variants/screebo/gpio.c b/src/mainboard/google/rex/variants/screebo/gpio.c new file mode 100644 index 0000000000..b6e346f5a4 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/gpio.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <types.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +DECLARE_CROS_GPIOS(cros_gpios); + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/rex/variants/screebo/include/variant/ec.h b/src/mainboard/google/rex/variants/screebo/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/rex/variants/screebo/include/variant/gpio.h b/src/mainboard/google/rex/variants/screebo/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc b/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc new file mode 100644 index 0000000000..eace2e443e --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt new file mode 100644 index 0000000000..fa247902ee --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt new file mode 100644 index 0000000000..96211370d9 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb new file mode 100644 index 0000000000..6c284b305b --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/meteorlake + + device domain 0 on + end + +end |