summaryrefslogtreecommitdiff
path: root/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/google/puff/variants/moonbuggy/overridetree.cb')
-rw-r--r--src/mainboard/google/puff/variants/moonbuggy/overridetree.cb64
1 files changed, 36 insertions, 28 deletions
diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
index a89c56dde6..ddbedac3f3 100644
--- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
+++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
@@ -243,7 +243,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on
- device pci 04.0 on
+ device ref dptf on
chip drivers/intel/dptf
## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU,
@@ -304,8 +304,8 @@ chip soc/intel/cannonlake
device generic 0 on end
end
- end # DPTF 0x1903
- device pci 14.0 on
+ end
+ device ref xhci on
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
@@ -385,29 +385,31 @@ chip soc/intel/cannonlake
end
end
end
- end # USB xHCI
- device pci 15.0 off
+ end
+ device ref i2c0 off
# RFU - Reserved for Future Use.
- end # I2C #0
- device pci 15.1 off end # I2C #1
- device pci 15.2 on
+ end
+ device ref i2c1 off end
+ device ref i2c2 on
+ # PCON PS175
chip drivers/i2c/generic
register "hid" = ""1AF80175""
register "name" = ""PS17""
register "desc" = ""Parade PS175""
device i2c 4a on end
end
- end # I2C #2, PCON PS175.
- device pci 15.3 on
+ end
+ device ref i2c3 on
+ # Realtek RTD2142
chip drivers/i2c/generic
register "hid" = ""10EC2142""
register "name" = ""RTD2""
register "desc" = ""Realtek RTD2142""
device i2c 4a on end
end
- end # I2C #3, Realtek RTD2142.
- device pci 16.0 on end # Management Engine Interface 1
- device pci 19.0 on
+ end
+ device ref heci1 on end
+ device ref i2c4 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
@@ -420,9 +422,10 @@ chip soc/intel/cannonlake
register "property_list[0].integer" = "1"
device i2c 1a on end
end
- end #I2C #4
- device pci 1a.0 off end # eMMC
- device pci 1c.6 on # PCI Root Port 7 (LAN)
+ end
+ device ref emmc off end
+ device ref pcie_rp7 on
+ # LAN
chip drivers/net # RTL8111H Ethernet NIC
register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7
@@ -431,26 +434,31 @@ chip soc/intel/cannonlake
device pci 00.0 on end
end
end
- device pci 1c.7 on # PCI Root Port 8 (WLAN)
+ device ref pcie_rp8 on
+ # WLAN
register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
end
- device pci 1d.0 on # PCI Root Port 9 (TPU)
+ device ref pcie_rp9 on
+ # TPU
register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
end
- device pci 1d.1 off end # PCI Root Port 10 (Not connected)
- device pci 1d.2 on end # PCI Root Port 11 (TPU1)
+ device ref pcie_rp10 off end
+ device ref pcie_rp11 on end
+ # TPU1
register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot
- device pci 1d.3 on end # PCI Root Port 12 (TPU0)
+ device ref pcie_rp12 on end
+ # TPU0
register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot
- device pci 1d.4 on # PCI Root Port 13 (X4 i350 NIC)
+ device ref pcie_rp13 on
+ # X4 i350 NIC
register "PcieRpSlotImplemented[12]" = "0" # Built-in
end
- device pci 1d.5 on end # PCI Root Port 14 (non-root)
- device pci 1d.6 on end # PCI Root Port 15 (non-root)
- device pci 1d.7 on end # PCI Root Port 16 (non-root)
- device pci 1e.0 on end # UART #0
- device pci 1e.1 on end # UART #1
- device pci 1e.3 off end # GSPI #1
+ device ref pcie_rp14 on end # non-root
+ device ref pcie_rp15 on end # non-root
+ device ref pcie_rp16 on end # non-root
+ device ref uart0 on end
+ device ref uart1 on end
+ device ref gspi1 off end
end
# VR Settings Configuration for 4 Domains