diff options
Diffstat (limited to 'src/mainboard/google/guybrush')
6 files changed, 19 insertions, 62 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 6b8c2b7caa..82956dc3e6 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -21,8 +21,8 @@ static const struct soc_amd_gpio base_gpio_table[] = { PAD_GPO(GPIO_3, LOW), /* SOC_PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_5, HIGH), + /* Unused */ + PAD_NC(GPIO_5), /* EN_PP3300_WLAN */ PAD_GPO(GPIO_6, HIGH), /* EN_PP3300_TCHPAD */ @@ -81,8 +81,8 @@ static const struct soc_amd_gpio base_gpio_table[] = { PAD_GPI(GPIO_67, PULL_NONE), /* EN_PP3300_TCHSCR */ PAD_GPO(GPIO_68, HIGH), - /* Unused */ - PAD_NC(GPIO_69), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_69, HIGH), /* Unused TP27 */ PAD_NC(GPIO_70), /* GPIO_71 - GPIO_73: Not available */ @@ -170,16 +170,16 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* Early GPIO configuration */ static const struct soc_amd_gpio early_gpio_table[] = { /* Assert all AUX reset lines */ - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_5, LOW), + /* Unused */ + PAD_NC(GPIO_5), /* WWAN_AUX_RESET_L */ PAD_GPO(GPIO_18, LOW), /* WLAN_AUX_RESET (ACTIVE HIGH) */ PAD_GPO(GPIO_29, HIGH), /* SSD_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), - /* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */ - PAD_NC(GPIO_69), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_69, LOW), /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */ PAD_NC(GPIO_70), @@ -278,16 +278,16 @@ static const struct soc_amd_gpio sleep_gpio_table[] = { /* PCIE_RST needs to be brought high before FSP-M runs */ static const struct soc_amd_gpio pcie_gpio_table[] = { /* Deassert all AUX_RESET lines & PCIE_RST */ - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_5, HIGH), + /* Unused */ + PAD_NC(GPIO_5), /* WWAN_AUX_RESET_L */ PAD_GPO(GPIO_18, HIGH), /* WLAN_AUX_RESET (ACTIVE HIGH) */ PAD_GPO(GPIO_29, LOW), /* SSD_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), - /* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */ - PAD_NC(GPIO_69), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_69, HIGH), /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */ PAD_NC(GPIO_70), /* PCIE_RST0_L */ diff --git a/src/mainboard/google/guybrush/variants/baseboard/helpers.c b/src/mainboard/google/guybrush/variants/baseboard/helpers.c index 36f7b05e70..fe30e15386 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/helpers.c +++ b/src/mainboard/google/guybrush/variants/baseboard/helpers.c @@ -11,5 +11,5 @@ bool __weak variant_has_pcie_wwan(void) uint8_t __weak variant_sd_aux_reset_gpio(void) { - return GPIO_5; + return GPIO_69; } diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index bf8e9997aa..6309ec2427 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -31,8 +31,6 @@ static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = { static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = { /* EN_PP5000_PEN */ PAD_GPO(GPIO_5, HIGH), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), /* GSC_SOC_INT_L */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* Unused */ @@ -42,9 +40,6 @@ static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = { }; static const struct soc_amd_gpio override_early_gpio_table[] = { - PAD_NC(GPIO_5), - /* BID >= 2: SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, LOW), /* BID == 1: SD_AUX_RESET_L */ PAD_GPO(GPIO_70, LOW), /* GSC_SOC_INT_L */ @@ -55,18 +50,10 @@ static const struct soc_amd_gpio override_early_gpio_table[] = { /* This table is used by guybrush variant with board version < 2. */ static const struct soc_amd_gpio bid1_pcie_gpio_table[] = { - PAD_NC(GPIO_5), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_70, HIGH), }; -/* This table is used by guybrush variant with board version < 2. */ -static const struct soc_amd_gpio bid2_pcie_gpio_table[] = { - PAD_NC(GPIO_5), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), -}; - const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -101,6 +88,5 @@ const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) return bid1_pcie_gpio_table; } - *size = ARRAY_SIZE(bid2_pcie_gpio_table); - return bid2_pcie_gpio_table; + return NULL; } diff --git a/src/mainboard/google/guybrush/variants/guybrush/variant.c b/src/mainboard/google/guybrush/variants/guybrush/variant.c index ded1351674..54ca6a0a7f 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/variant.c +++ b/src/mainboard/google/guybrush/variants/guybrush/variant.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <boardid.h> #include <device/device.h> #include <soc/gpio.h> @@ -11,5 +12,5 @@ bool variant_has_pcie_wwan(void) uint8_t variant_sd_aux_reset_gpio(void) { - return GPIO_69; + return board_id() == 1 ? GPIO_70 : GPIO_69; } diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 4d6e045d97..2c502df246 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -16,8 +16,6 @@ static const struct soc_amd_gpio bid1_override_gpio_table[] = { PAD_NC(GPIO_18), /* LCD_PRIVACY_PCH */ PAD_GPO(GPIO_5, HIGH), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), /* GSC_SOC_INT_L */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* Unused */ @@ -34,30 +32,16 @@ static const struct soc_amd_gpio bid2_override_gpio_table[] = { PAD_NC(GPIO_17), /* LCD_PRIVACY_PCH */ PAD_GPO(GPIO_18, HIGH), - /* Unused */ - PAD_NC(GPIO_69), }; static const struct soc_amd_gpio override_early_gpio_table[] = { /* BID == 1: GSC_SOC_INT_L, BID > 1: Unused */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), PAD_NC(GPIO_18), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, LOW), -}; - -/* This table is used by nipperkin variant with board version < 2. */ -static const struct soc_amd_gpio bid1_override_pcie_gpio_table[] = { - PAD_NC(GPIO_5), - PAD_NC(GPIO_18), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), }; -/* This table is used by nipperkin variant with board version >= 2. */ -static const struct soc_amd_gpio bid2_override_pcie_gpio_table[] = { +static const struct soc_amd_gpio override_pcie_gpio_table[] = { PAD_NC(GPIO_18), - PAD_NC(GPIO_69), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -81,13 +65,6 @@ const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size) const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) { - uint32_t board_version = board_id(); - - if (board_version < 2) { - *size = ARRAY_SIZE(bid1_override_pcie_gpio_table); - return bid1_override_pcie_gpio_table; - } - - *size = ARRAY_SIZE(bid2_override_pcie_gpio_table); - return bid2_override_pcie_gpio_table; + *size = ARRAY_SIZE(override_pcie_gpio_table); + return override_pcie_gpio_table; } diff --git a/src/mainboard/google/guybrush/variants/nipperkin/variant.c b/src/mainboard/google/guybrush/variants/nipperkin/variant.c index 917857c3ac..c53d691b5e 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/variant.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/variant.c @@ -10,10 +10,3 @@ void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors) dxio_descriptors[WLAN].link_aspm_L1_1 = false; dxio_descriptors[WLAN].link_aspm_L1_2 = false; } - -uint8_t variant_sd_aux_reset_gpio(void) -{ - uint32_t board_ver = board_id(); - - return (board_ver < 2) ? GPIO_69 : GPIO_5; -} |