diff options
Diffstat (limited to 'src/mainboard/google/guybrush')
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 10 | ||||
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h | 1 |
2 files changed, 5 insertions, 6 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 848fd935e3..49ff8dd3c7 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -44,12 +44,10 @@ chip soc/amd/cezanne /* * b/218874489 - This should really be ESPI_VW_IRQ_LEVEL_HIGH, - * but eSPI gets configured in verstage which is in RO. - * We have already locked RO for guybrush devices so we need - * make it so x86 coreboot re-initializes the vw_irq_polarity. - * This leaves another problem, verstage also runs in S0i3, but - * we don't run any other x86 coreboot stages, so we need to - * figure out a way to reset the eSPI polarity. + * but eSPI gets configured in verstage which is in RO, and the + * RO is already locked down. As a workaround, the EC fw has + * been modified to use active low signalling for the + * interrupts that require it. */ .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1), }" diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h index 643c534189..83a4b2fe8c 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h @@ -63,6 +63,7 @@ #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Level, ActiveLow, Shared) {1} /* Enable EC sync interrupt */ #define EC_ENABLE_SYNC_IRQ_GPIO |