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path: root/src/mainboard/google/guybrush/variants/guybrush/gpio.c
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Diffstat (limited to 'src/mainboard/google/guybrush/variants/guybrush/gpio.c')
-rw-r--r--src/mainboard/google/guybrush/variants/guybrush/gpio.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
index e90f4a3a89..fe2dcd117e 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c
+++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
@@ -44,10 +44,6 @@ static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = {
static const struct soc_amd_gpio override_early_gpio_table[] = {
/* BID == 1: SD_AUX_RESET_L */
PAD_GPO(GPIO_70, LOW),
- /* GSC_SOC_INT_L */
- PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
- /* Unused */
- PAD_NC(GPIO_85),
};
/* This table is used by guybrush variant with board version < 2. */
@@ -56,6 +52,15 @@ static const struct soc_amd_gpio bid1_pcie_gpio_table[] = {
PAD_GPO(GPIO_70, HIGH),
};
+static const struct soc_amd_gpio tpm_gpio_table[] = {
+ /* I2C3_SCL */
+ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
+ /* I2C3_SDA */
+ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
+ /* GSC_SOC_INT_L */
+ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
+};
+
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
{
uint32_t board_version = board_id();
@@ -92,3 +97,9 @@ const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
return NULL;
}
+
+const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size)
+{
+ *size = ARRAY_SIZE(tpm_gpio_table);
+ return tpm_gpio_table;
+}