diff options
Diffstat (limited to 'src/mainboard/google/guybrush/variants/baseboard/gpio.c')
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/gpio.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 1ee70dae33..beb654f013 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -268,7 +268,7 @@ static const struct soc_amd_gpio bootblock_gpio_table[] = { }; /* PCIE_RST needs to be brought high before FSP-M runs */ -static const struct soc_amd_gpio pcie_gpio_table[] = { +static const struct soc_amd_gpio romstage_gpio_table[] = { /* Deassert all AUX_RESET lines & PCIE_RST */ /* Unused */ PAD_NC(GPIO_5), @@ -286,10 +286,10 @@ static const struct soc_amd_gpio pcie_gpio_table[] = { PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), }; -const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size) +const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size) { - *size = ARRAY_SIZE(pcie_gpio_table); - return pcie_gpio_table; + *size = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } const struct soc_amd_gpio *__weak variant_bootblock_gpio_table(size_t *size) @@ -322,7 +322,7 @@ const struct soc_amd_gpio * __weak variant_bootblock_override_gpio_table(size_t return NULL; } -const struct soc_amd_gpio * __weak variant_pcie_override_gpio_table(size_t *size) +const struct soc_amd_gpio * __weak variant_romstage_override_gpio_table(size_t *size) { *size = 0; return NULL; |