diff options
Diffstat (limited to 'src/mainboard/google/fatcat')
4 files changed, 794 insertions, 39 deletions
diff --git a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk index ac6779c131..eb361dfe89 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk @@ -5,4 +5,5 @@ romstage-y += gpio.c romstage-y += memory.c romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c -ramstage-y += variant.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index 0e34c13201..46ef6a8b83 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -2,15 +2,153 @@ #include <baseboard/variants.h> #include <bootstate.h> +#include <console/console.h> #include <fw_config.h> #include <gpio.h> +#include <inttypes.h> -#define GPIO_CONFIGURE_PADS(a) gpio_configure_pads(a, ARRAY_SIZE(a)) +/* t: base table; o: override table */ +#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o)) +/* t: table */ +#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t)) + +static const struct pad_config i2s_enable_pads[] = { + /* I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), + /* I2S0_SCLK_HDR */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + /* I2S0_SFRM_HDR */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + /* I2S0_TXD_HDR */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + /* I2S0_RXD_HDR */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), + /* I2S1_SCLK_HDR */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF6), + /* I2S1_SFRM_HDR */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF6), + /* I2S1_TXD_HDR */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF6), + /* I2S1_RXD_HDR */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF6), + + /* DMIC_CLK */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3), + /* DMIC_DATA */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3), + + /* DMIC_CLK */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), + /* DMIC_DATA */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), +}; + +static const struct pad_config hda_enable_pads[] = { + /* HDA_BCLK */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + /* HDA_SYNC */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), + /* HDA_SDO */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), + /* HDA_SDI_0 */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), + /* HDA_RST_B */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + /* HDA_SDI_1 */ + PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1), + + /* DMIC_CLK */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), + /* DMIC_DATA */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), +}; + +static const struct pad_config sndw_external_codec_enable_pads[] = { + /* Soundwire - External codec - JE Header */ + /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* SNDW3_DATA0 */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* SNDW0_CLK */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3), + /* SNDW0_DATA */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3), + /* SNDW2_CLK */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2), + /* SNDW2_DATA */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2), + /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), + /* SNDW1_DATA */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), + + /* GPP_D13: RST_HP_L */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), +}; + +static const struct pad_config sndw_alc722_enable_pads[] = { + /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* SNDW3_DATA0 */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* SNDW3_DATA1 */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1), + /* SNDW3_DATA2 */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1), + /* DMIC_CLK_A0 */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), + /* DMIC_DATA_0 */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), + /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), + /* SNDW1_DATA */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), + + /* DMIC_CLK */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3), + /* DMIC_DATA */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3), +}; + +static const struct pad_config audio_disable_pads[] = { + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_NC(GPP_S02, NONE), + PAD_NC(GPP_S03, NONE), + PAD_NC(GPP_S04, NONE), + PAD_NC(GPP_S05, NONE), + PAD_NC(GPP_S06, NONE), + PAD_NC(GPP_S07, NONE), + PAD_NC(GPP_D09, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), +}; static const struct pad_config pre_mem_x1slot_pads[] = { /* GPP_A08: X1_PCIE_SLOT_PWR_EN */ PAD_CFG_GPO(GPP_A08, 0, PLTRST), }; +static const struct pad_config x1slot_pads[] = { + /* GPP_A08: X1_PCIE_SLOT_PWR_EN */ + PAD_CFG_GPO(GPP_A08, 1, PLTRST), + /* GPP_D19: X1_DT_PCIE_RST_N */ + PAD_CFG_GPO(GPP_D19, 1, PLTRST), + /* GPP_B25: X1_SLOT_WAKE_N */ + PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL), +}; + +static const struct pad_config x1slot_disable_pads[] = { + /* GPP_A08: X1_PCIE_SLOT_PWR_EN */ + PAD_CFG_GPO(GPP_A08, 0, PLTRST), + /* GPP_D19: X1_DT_PCIE_RST_N */ + PAD_NC(GPP_D19, NONE), + /* GPP_B25: X1_SLOT_WAKE_N */ + PAD_NC(GPP_B25, NONE) +}; /* * WWAN: power sequence requires three stages: @@ -36,61 +174,316 @@ static const struct pad_config pre_mem_wwan_pwr_seq2_pads[] = { PAD_CFG_GPO(GPP_A09, 1, PLTRST), }; -/* gen4 NVME: at the top M.2 slot */ +static const struct pad_config wwan_pwr_seq3_pads[] = { + /* GPP_D03: M.2_WWAN_PERST_GPIO_N */ + PAD_CFG_GPO(GPP_D03, 1, PLTRST), + /* GPP_B20: M.2_WWAN_RST_N */ + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + /* GPP_E02: WWAN_WAKE_GPIO_N */ + PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL), +}; + +static const struct pad_config wwan_disable_pads[] = { + /* GPP_A09: M.2_WWAN_FCP_OFF_N */ + PAD_NC(GPP_A09, NONE), + /* GPP_D03: M.2_WWAN_PERST_GPIO_N */ + PAD_NC(GPP_D03, NONE), + /* GPP_B20: M.2_WWAN_RST_N */ + PAD_NC(GPP_B20, NONE), + /* GPP_H16: WWAN_PWREN */ + PAD_NC(GPP_H16, NONE), + /* GPP_A10: M.2_WWAN_DISABLE_N */ + PAD_NC(GPP_A10, NONE), + /* GPP_E02: WWAN_WAKE_GPIO_N */ + PAD_NC(GPP_E02, NONE), +}; + +/* Gen4 NVME: at the top M.2 slot */ static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = { /* GPP_B10: GEN4_SSD_PWREN */ PAD_CFG_GPO(GPP_B10, 0, PLTRST), }; -/* gen5 NVME: at the bottom M.2 slot */ +static const struct pad_config gen4_ssd_pads[] = { + /* GPP_B10: GEN4_SSD_PWREN */ + PAD_CFG_GPO(GPP_B10, 1, PLTRST), + /* GPP_B09: M2_GEN4_SSD_RESET_N */ + PAD_CFG_GPO(GPP_B09, 1, PLTRST), +}; + +/* Gen5 NVME: at the bottom M.2 slot */ static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = { /* GPP_B16: GEN5_SSD_PWREN */ PAD_CFG_GPO(GPP_B16, 0, PLTRST), }; +static const struct pad_config gen5_ssd_pads[] = { + /* GPP_B16: GEN5_SSD_PWREN */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + /* GPP_E03: M2_GEN5_SSD_RESET_N */ + PAD_CFG_GPO(GPP_E03, 1, PLTRST), +}; + /* camera1: WFC */ static const struct pad_config pre_mem_wfc_camera_pwr_pads[] = { /* GPP_C05: CRD1_PWREN */ PAD_CFG_GPO(GPP_C05, 0, PLTRST), }; +static const struct pad_config wfc_camera_enable_pads[] = { + /* GPP_C05: CRD1_PWREN */ + PAD_CFG_GPO(GPP_C05, 1, PLTRST), + /* GPP_D04: IMGCLKOUT_0 */ + PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1), +}; + +static const struct pad_config wfc_camera_disable_pads[] = { + /* GPP_C05: CRD1_PWREN */ + PAD_NC(GPP_C05, NONE), + /* GPP_D04: IMGCLKOUT_0 */ + PAD_NC(GPP_D04, NONE), +}; + /* camera2: UFC */ static const struct pad_config pre_mem_ufc_camera_pwr_pads[] = { /* GPP_C08: CRD2_PWREN */ PAD_CFG_GPO(GPP_C08, 0, PLTRST), }; +static const struct pad_config ufc_camera_enable_pads[] = { + /* GPP_C08: CRD2_PWREN */ + PAD_CFG_GPO(GPP_C08, 1, PLTRST), + /* GPP_D00: IMGCLKOUT_1 */ + PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), +}; + +static const struct pad_config ufc_camera_disable_pads[] = { + /* GPP_C08: CRD2_PWREN */ + PAD_NC(GPP_C08, NONE), + /* GPP_D00: IMGCLKOUT_1 */ + PAD_NC(GPP_D00, NONE), +}; + +static const struct pad_config peg_x4slot_wake_disable_pads[] = { + /* GPP_D24: PEG_SLOT_WAKE_N */ + PAD_NC(GPP_D24, NONE), + /* GPP_D25: X4_SLOT_WAKE_N */ + PAD_NC(GPP_D25, NONE), +}; + +static const struct pad_config pcie_wlan_enable_pads[] = { + /* GPP_A11: WLAN_RST_N */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), + /* GPP_A12: WIFI_WAKE_N */ + PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL), +}; + +static const struct pad_config pcie_wlan_disable_pads[] = { + /* GPP_A11: WLAN_RST_N */ + PAD_NC(GPP_A11, NONE), + /* GPP_A12: WIFI_WAKE_N */ + PAD_NC(GPP_A12, NONE), +}; + +static const struct pad_config cnvi_enable_pads[] = { + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), + /* GPP_F04: CNV_RF_RESET_R_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05: CRF_CLKREQ_R */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), + /* GPP_A16: BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A16, 1, DEEP), + /* GPP_A17: WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_A17, 1, DEEP), +}; + +static const struct pad_config cnvi_disable_pads[] = { + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_NC(GPP_F00, NONE), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + PAD_NC(GPP_F01, NONE), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + PAD_NC(GPP_F02, NONE), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_NC(GPP_F03, NONE), + /* GPP_F04: CNV_RF_RESET_R_N */ + PAD_NC(GPP_F04, NONE), + /* GPP_F05: CRF_CLKREQ_R */ + PAD_NC(GPP_F05, NONE), + + /* GPP_A16: BT_RF_KILL_N */ + PAD_NC(GPP_A16, NONE), + /* GPP_A17: WIFI_RF_KILL_N */ + PAD_NC(GPP_A17, NONE), +}; + +static const struct pad_config touchscreen_disable_pads[] = { + /* GPP_F08: TCH_PNL1_PWR_EN */ + PAD_CFG_GPO(GPP_F08, 0, PLTRST), + + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF8: I2C4_SCL */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF8: I2C4 SDA */ + PAD_NC(GPP_E13, NONE), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ + PAD_NC(GPP_E18, NONE), +}; + +static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = { + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF8: I2C4_SCL */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF8: I2C4 SDA */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE), +}; + +static const struct pad_config touchscreen_thc_i2c_enable_pads[] = { + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF1: THC I2C0_SCL */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF1: THC I2C0 SDA */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE), +}; + +static const struct pad_config touchscreen_gspi_enable_pads[] = { + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 NF5: GSPI0 */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF5: GSPI0 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF5), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF5: GSPI0 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF5), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 NF5: GSPI0 */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT) +}; + +static const struct pad_config touchscreen_thc_spi_enable_pads[] = { + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 NF3: THC HID-SPI */ + /* THC NOTE: use GPO instead of NF for THC0 Rst */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 NF3: THC HID-SPI */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), +}; + +static const struct pad_config touchpad_thc_i2c_enable_pads[] = { + /* GPP_F12: NF1: thc_i2c1_scl */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* GPP_F13: NF1: thc_i2c1_sda */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +}; + +static const struct pad_config touchpad_lpss_i2c_enable_pads[] = { + /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), + /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), + /* GPP_F18: TCH_PAD_INT_N */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), +}; + +static const struct pad_config touchpad_i2c_disable_pads[] = { + /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ + PAD_NC(GPP_F12, NONE), + /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ + PAD_NC(GPP_F13, NONE), + /* GPP_F18: TCH_PAD_INT_N */ + PAD_NC(GPP_F18, NONE), +}; + void fw_config_configure_pre_mem_gpio(void) { - if (fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_PCIE)) || - fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_USB))) { - GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads); + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Existing"); + return; } - if (fw_config_probe(FW_CONFIG(WFC, WFC_MIPI))) { + if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT))) + GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads); + + if (fw_config_probe(FW_CONFIG(WFC, WFC_MIPI))) GPIO_CONFIGURE_PADS(pre_mem_wfc_camera_pwr_pads); - } - if (fw_config_probe(FW_CONFIG(UFC, UFC_MIPI))) { + if (fw_config_probe(FW_CONFIG(UFC, UFC_MIPI))) GPIO_CONFIGURE_PADS(pre_mem_ufc_camera_pwr_pads); - } if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) { GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) { GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads); - } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { - /* TODO */ + /* TODO: else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) + */ } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads); /* TODO for UFS */ } - if (fw_config_probe(FW_CONFIG(SD, SD_GENSYS)) || - fw_config_probe(FW_CONFIG(SD, SD_BAYHUB))) { + if (!fw_config_probe(FW_CONFIG(SD, SD_NONE))) GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads); - } + /* * NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM * FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V @@ -101,8 +494,90 @@ void fw_config_configure_pre_mem_gpio(void) * stages are preserved at this time to guarantee the sequence shown in the * datasheet timing diagram. */ + if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT))) + GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads); +} + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Existing"); + return; + } + + if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) { + GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads); + } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) { + GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads); + /* TODO: else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) + */ + } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { + GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads); + /* TODO for UFS */ + } + + if (fw_config_probe(FW_CONFIG(WFC, WFC_MIPI))) + GPIO_PADBASED_OVERRIDE(padbased_table, wfc_camera_enable_pads); + else + GPIO_PADBASED_OVERRIDE(padbased_table, wfc_camera_disable_pads); + + if (fw_config_probe(FW_CONFIG(UFC, UFC_MIPI))) + GPIO_PADBASED_OVERRIDE(padbased_table, ufc_camera_enable_pads); + else + GPIO_PADBASED_OVERRIDE(padbased_table, ufc_camera_disable_pads); + + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) + GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads); + else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S))) + GPIO_PADBASED_OVERRIDE(padbased_table, i2s_enable_pads); + else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98373_ALC5682_SNDW))) + GPIO_PADBASED_OVERRIDE(padbased_table, sndw_external_codec_enable_pads); + else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW))) + GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc722_enable_pads); + else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) + GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads); + + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_6)) || + fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_7))) { + GPIO_PADBASED_OVERRIDE(padbased_table, pcie_wlan_enable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_disable_pads); + } else if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) || + fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) { + GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_enable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, pcie_wlan_disable_pads); + } + if (fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_PCIE)) || fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_USB))) { - GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, wwan_pwr_seq3_pads); + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, wwan_disable_pads); } + + if (fw_config_probe(FW_CONFIG(SD, SD_NONE))) + GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_disable_pads); + else + GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads); + + if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) + GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads); + else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) + GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_thc_i2c_enable_pads); + else + GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads); + + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C))) + GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_lpss_i2c_enable_pads); + else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) + GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads); + else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) + GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_gspi_enable_pads); + else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) + GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads); + else + GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads); + + /* NOTE: disable PEG (x8 slot) and x4 slot wake for now */ + GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads); } diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index f89bfd8783..a7107bfe92 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -66,10 +66,43 @@ end chip soc/intel/pantherlake + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C3 + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0 + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 / WWAN with rework + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #2 / M.2 WWAN with rework + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN" + + # Enable EDP in PortA + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + }" + + # TCSS USB3 + register "tcss_aux_ori" = "1" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, }" # Intel Common SoC Config @@ -78,6 +111,9 @@ chip soc/intel/pantherlake #+-------------------+---------------------------+ #| I2C1 | Camera(CRD1) | #| I2C2 | Camera(CRD2) | + #| I2C3 | Audio, TPM(cr50) | + #| I2C4 | Touchscreen | + #| I2C5 | Touchpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -87,6 +123,16 @@ chip soc/intel/pantherlake .i2c[2] = { .speed = I2C_SPEED_FAST, }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, }" device domain 0 on @@ -105,6 +151,145 @@ chip soc/intel/pantherlake end end + device ref iaa off end + + device ref thc0 on + probe TOUCHSCREEN TOUCHSCREEN_THC_SPI + probe TOUCHSCREEN TOUCHSCREEN_THC_I2C + # THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled. + probe TOUCHPAD TOUCHPAD_THC_I2C + end + device ref thc1 on + probe TOUCHPAD TOUCHPAD_THC_I2C + end + + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C3"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref tcss_usb3_port3 on end + end + end + end + end + + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port1 as dfp[1].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port3 as dfp[1].typec_port + device generic 0 on end + end + end + + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C3"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(6, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(7, 1)" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on end + end + end + end + end + device ref pcie_rp2 on probe CELLULAR CELLULAR_PCIE register "pcie_rp[PCIE_RP(2)]" = "{ @@ -119,9 +304,7 @@ chip soc/intel/pantherlake register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "skip_on_off_support" = "true" register "use_rp_mutex" = "true" - device generic 0 alias rp2_rtd3 on - probe CELLULAR CELLULAR_PCIE - end + device generic 0 alias rp2_rtd3 on end end chip drivers/wwan/fm register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A09)" @@ -130,9 +313,7 @@ chip soc/intel/pantherlake register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E02)" register "add_acpi_dma_property" = "true" use rp2_rtd3 as rtd3dev - device generic 0 on - probe CELLULAR CELLULAR_PCIE - end + device generic 0 on end end end # WWAN device ref pcie_rp3 on @@ -150,12 +331,29 @@ chip soc/intel/pantherlake register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)" register "reset_delay_ms" = "20" register "srcclk_pin" = "2" - device generic 0 on - probe SD SD_GENSYS - probe SD SD_BAYHUB - end + device generic 0 on end end end # PCIE x1 slot + device ref pcie_rp4 on + probe WIFI WIFI_PCIE_6 + probe WIFI WIFI_PCIE_7 + register "pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "4" + device pci 00.0 on end + end + chip drivers/wifi/generic + register "add_acpi_dma_property" = "true" + register "wake" = "GPE0_DW0_12" # GPP_A12 + use usb2_port7 as bluetooth_companion + device pci 00.0 on end + end + end # discrete WLAN device ref pcie_rp5 on probe STORAGE STORAGE_NVME_GEN4 probe STORAGE STORAGE_UNKNOWN @@ -169,10 +367,7 @@ chip soc/intel/pantherlake register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)" register "srcclk_pin" = "6" - device generic 0 on - probe STORAGE STORAGE_NVME_GEN4 - probe STORAGE STORAGE_UNKNOWN - end + device generic 0 on end end end # Gen4 M.2 SSD device ref pcie_rp9 on @@ -188,18 +383,23 @@ chip soc/intel/pantherlake register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)" register "srcclk_pin" = "1" - device generic 0 on - probe STORAGE STORAGE_NVME_GEN5 - probe STORAGE STORAGE_UNKNOWN - end + device generic 0 on end end end # Gen5 M.2 SSD - + device ref cnvi_wifi on + probe WIFI WIFI_CNVI_6 + probe WIFI WIFI_CNVI_7 + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end # CNVi # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled. # TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways. device ref i2c0 on end device ref i2c1 on - probe WFC WFC_MIPI chip drivers/intel/mipi_camera register "acpi_hid" = ""OVTIDB10"" register "acpi_uid" = "0" @@ -270,9 +470,8 @@ chip soc/intel/pantherlake probe WFC WFC_MIPI end end - end + end # I2C1 device ref i2c2 on - probe UFC UFC_MIPI chip drivers/intel/mipi_camera register "acpi_hid" = ""OVTIDB10"" register "acpi_uid" = "0" @@ -343,6 +542,74 @@ chip soc/intel/pantherlake probe UFC UFC_MIPI end end + end # I2C2 + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F17)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO AUDIO_MAX98360_ALC5682I_I2S + end + end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D15_IRQ)" + device i2c 50 on end + end + end # I2C3 + device ref i2c4 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6918"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 16 on + probe TOUCHSCREEN TOUCHSCREEN_LPSS_I2C + end + end + end # I2C4 + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""HFW68H"" + register "generic.desc" = ""Hynitron TOUCHPAD"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)" + register "generic.uid" = "5" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on + probe TOUCHPAD TOUCHPAD_LPSS_I2C + end + end + end # I2C5 + + device ref smbus on end + device ref npk on end + device ref hda on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 1 ID 1 + register "desc" = ""Headset Codec"" + device generic 1.1 on + probe AUDIO AUDIO_ALC722_SNDW + end + end + end + end end end end diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c index 8893753a9a..086f709bff 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/variant.c +++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c @@ -9,3 +9,15 @@ const char *get_wifi_sar_cbfs_filename(void) { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); } + +void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) +{ + config->cnvi_wifi_core = false; + config->cnvi_bt_core = false; + /* CNVi */ + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) || + fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) { + config->cnvi_wifi_core = true; + config->cnvi_bt_core = true; + } +} |