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-rw-r--r--src/mainboard/google/drallion/variants/drallion/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index ed44f4fec1..6ecb689790 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -38,6 +38,8 @@ chip soc/intel/cannonlake
register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmSlpAMinAssert" = "4" # 2s
register "PchUnlockGpioPads" = "1"
+ # USB2 PHY Power gating
+ register "PchUsb2PhySusPgDisable" = "1"
register "speed_shift_enable" = "1"
register "psys_pmax" = "140"