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-rw-r--r--src/mainboard/google/dedede/variants/bugzzy/overridetree.cb3
-rw-r--r--src/mainboard/google/dedede/variants/galtic/overridetree.cb3
-rw-r--r--src/mainboard/google/dedede/variants/magolor/overridetree.cb3
-rw-r--r--src/mainboard/google/dedede/variants/metaknight/overridetree.cb3
4 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index 30e5e454dc..7496428cf7 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -2,9 +2,6 @@ chip soc/intel/jasperlake
# MIPI display panel
register "DdiPortAConfig" = "2" # DdiPortMipiDsi
- # Core Display Clock Frequency selection
- register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
# Enable Acoustic noise mitigation and set slew rate to 1/8
# Rest of the parameters are 0 by default.
register "AcousticNoiseMitigation" = "1"
diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
index 73a5f49a37..fcf66f2bdb 100644
--- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
@@ -75,9 +75,6 @@ chip soc/intel/jasperlake
register "tcc_offset" = "8" # TCC of 97C
- # Core Display Clock Frequency selection
- register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
device domain 0 on
device pci 04.0 on
# Default DPTF Policy for all Dedede boards if not overridden
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index e0af22dd49..66fc4ea02f 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -108,9 +108,6 @@ chip soc/intel/jasperlake
register "SlowSlewRate" = "SlewRateFastBy8"
register "FastPkgCRampDisable" = "1"
- # Core Display Clock Frequency selection
- register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf
diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
index 06da2d48c3..bb4762f82c 100644
--- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
@@ -69,9 +69,6 @@ chip soc/intel/jasperlake
.tdp_pl2_override = 12,
}"
- # Core Display Clock Frequency selection
- register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf