diff options
Diffstat (limited to 'src/mainboard/google/cyan/variants')
10 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/google/cyan/variants/banon/romstage.c b/src/mainboard/google/cyan/variants/banon/romstage.c index 7dcf6222d9..a711e19eed 100644 --- a/src/mainboard/google/cyan/variants/banon/romstage.c +++ b/src/mainboard/google/cyan/variants/banon/romstage.c @@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) * RAMID = 12 - 2GiB Micron MT52L256M32D1PF */ if (ram_id == 4 || ram_id == 12) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c index a126a4881a..a28783817c 100644 --- a/src/mainboard/google/cyan/variants/celes/ramstage.c +++ b/src/mainboard/google/cyan/variants/celes/ramstage.c @@ -5,7 +5,6 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) { if (SocStepping() >= SocD0) { - //Follow Intel recommendation to set //BSW D-stepping PERPORTRXISET 2 (low strength) params->Usb2Port0PerPortPeTxiSet = 7; diff --git a/src/mainboard/google/cyan/variants/edgar/romstage.c b/src/mainboard/google/cyan/variants/edgar/romstage.c index 7b1d8cce99..af55b8aa9b 100644 --- a/src/mainboard/google/cyan/variants/edgar/romstage.c +++ b/src/mainboard/google/cyan/variants/edgar/romstage.c @@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) * RAMID = 7 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 5 || ram_id == 7) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/kefka/ramstage.c b/src/mainboard/google/cyan/variants/kefka/ramstage.c index e1fd33aecf..96d53c25ef 100644 --- a/src/mainboard/google/cyan/variants/kefka/ramstage.c +++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c @@ -5,7 +5,6 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) { if (SocStepping() >= SocD0) { - //Follow Intel recommendation to set //BSW D-stepping PERPORTRXISET 2 (low strength) params->D0Usb2Port0PerPortRXISet = 2; diff --git a/src/mainboard/google/cyan/variants/kefka/romstage.c b/src/mainboard/google/cyan/variants/kefka/romstage.c index 9492b84b51..d5e88830af 100644 --- a/src/mainboard/google/cyan/variants/kefka/romstage.c +++ b/src/mainboard/google/cyan/variants/kefka/romstage.c @@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) * RAMID = 3 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 2 || ram_id == 3) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/reks/romstage.c b/src/mainboard/google/cyan/variants/reks/romstage.c index c8fd30bf83..4b817e594e 100644 --- a/src/mainboard/google/cyan/variants/reks/romstage.c +++ b/src/mainboard/google/cyan/variants/reks/romstage.c @@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) * RAMID = 2 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 2 || ram_id == 0xA) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/relm/romstage.c b/src/mainboard/google/cyan/variants/relm/romstage.c index c8fd30bf83..4b817e594e 100644 --- a/src/mainboard/google/cyan/variants/relm/romstage.c +++ b/src/mainboard/google/cyan/variants/relm/romstage.c @@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) * RAMID = 2 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 2 || ram_id == 0xA) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/setzer/romstage.c b/src/mainboard/google/cyan/variants/setzer/romstage.c index e8c3c1c3b1..21e1569eff 100644 --- a/src/mainboard/google/cyan/variants/setzer/romstage.c +++ b/src/mainboard/google/cyan/variants/setzer/romstage.c @@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) * RAMID = 5 - 2GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 4 || ram_id == 5) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/terra/romstage.c b/src/mainboard/google/cyan/variants/terra/romstage.c index 5bdd7fe04f..531f1ead15 100644 --- a/src/mainboard/google/cyan/variants/terra/romstage.c +++ b/src/mainboard/google/cyan/variants/terra/romstage.c @@ -13,7 +13,6 @@ void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) * RAMID = 11 - 4GiB Micron MT52L256M32D1PF-107 */ if (ram_id == 3 || ram_id == 11) { - /* * For new micron part, it requires read/receive * enable training before sending cmds to get MR8. diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index ede6229a9b..13cc6398bf 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -237,5 +237,4 @@ static struct soc_gpio_config gpio_config = { struct soc_gpio_config *mainboard_get_gpios(void) { return &gpio_config; - } |