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-rw-r--r--src/mainboard/google/brya/Kconfig2
-rw-r--r--src/mainboard/google/brya/dsdt.asl2
-rw-r--r--src/mainboard/google/brya/variants/anahera/overridetree.cb2
-rw-r--r--src/mainboard/google/brya/variants/anahera4es/overridetree.cb2
-rw-r--r--src/mainboard/google/brya/variants/brya0/overridetree.cb2
-rw-r--r--src/mainboard/google/brya/variants/brya4es/overridetree.cb2
-rw-r--r--src/mainboard/google/brya/variants/redrix/overridetree.cb2
-rw-r--r--src/mainboard/google/brya/variants/redrix4es/overridetree.cb2
-rw-r--r--src/mainboard/google/brya/variants/skolas4es/overridetree.cb2
-rw-r--r--src/mainboard/google/brya/variants/taeko/overridetree.cb2
-rw-r--r--src/mainboard/google/brya/variants/taeko4es/overridetree.cb2
-rw-r--r--src/mainboard/google/brya/variants/vell/overridetree.cb2
12 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index b985be20a9..228aecdff7 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -97,7 +97,7 @@ config CHROMEOS
select HAS_RECOVERY_MRC_CACHE
config CHROMEOS_WIFI_SAR
- bool "Enable SAR options for Chrome OS build"
+ bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS
select DSAR_ENABLE
select GEO_SAR_ENABLE
diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl
index de3337f399..ab4d210551 100644
--- a/src/mainboard/google/brya/dsdt.asl
+++ b/src/mainboard/google/brya/dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock(
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index 48a1fdd42d..e5c2e960b9 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -79,7 +79,7 @@ chip soc/intel/alderlake
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
- # Use Chrome OS privacy screen _HID
+ # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"
diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
index cac72995bc..63fb2a901d 100644
--- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
@@ -71,7 +71,7 @@ chip soc/intel/alderlake
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
- # Use Chrome OS privacy screen _HID
+ # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index a94410354b..6ac469af1f 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -570,7 +570,7 @@ chip soc/intel/alderlake
end
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
- register "desc" = ""Chrome OS HPS""
+ register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
index 9d9233b9d5..eed577710b 100644
--- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
@@ -571,7 +571,7 @@ chip soc/intel/alderlake
end
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
- register "desc" = ""Chrome OS HPS""
+ register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 4d7d6a5d13..3b92b63b49 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -99,7 +99,7 @@ chip soc/intel/alderlake
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
- # Use Chrome OS privacy screen _HID
+ # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
index 9a0eb1f6e8..60eb8a3d0d 100644
--- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
@@ -85,7 +85,7 @@ chip soc/intel/alderlake
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
- # Use Chrome OS privacy screen _HID
+ # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"
diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
index 6f0eb2168e..3280b4be4f 100644
--- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
@@ -570,7 +570,7 @@ chip soc/intel/alderlake
end
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
- register "desc" = ""Chrome OS HPS""
+ register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 5a964c6672..9a4de9393c 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -416,7 +416,7 @@ chip soc/intel/alderlake
device ref i2c2 on
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
- register "desc" = ""Chrome OS HPS""
+ register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
index f1074de74d..3ec57e47c8 100644
--- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
@@ -320,7 +320,7 @@ chip soc/intel/alderlake
device ref i2c2 on
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
- register "desc" = ""Chrome OS HPS""
+ register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 903b67f209..d8ef5096cc 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -94,7 +94,7 @@ chip soc/intel/alderlake
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
- # Use Chrome OS privacy screen _HID
+ # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"