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-rw-r--r--src/mainboard/google/brya/variants/nereid/gpio.c4
-rw-r--r--src/mainboard/google/brya/variants/nereid/overridetree.cb6
2 files changed, 9 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/nereid/gpio.c b/src/mainboard/google/brya/variants/nereid/gpio.c
index 0f68ecf3b7..f9ef8c9953 100644
--- a/src/mainboard/google/brya/variants/nereid/gpio.c
+++ b/src/mainboard/google/brya/variants/nereid/gpio.c
@@ -9,6 +9,10 @@
static const struct pad_config override_gpio_table[] = {
/* A8 : WWAN_RF_DISABLE_ODL */
PAD_NC(GPP_A8, NONE),
+ /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
+ PAD_CFG_GPO(GPP_A21, 0, DEEP),
+ /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
+ PAD_CFG_GPO(GPP_A22, 1, DEEP),
/* B5 : SOC_I2C_SUB_SDA */
PAD_NC(GPP_B5, NONE),
diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb
index 50c98ceed7..806c74d768 100644
--- a/src/mainboard/google/brya/variants/nereid/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb
@@ -9,8 +9,12 @@ end
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
+ # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
+ # Bit 2 - C1 has a redriver which does SBU muxing.
+ # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
+ register "tcss_aux_ori" = "1"
+
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
- register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN