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-rw-r--r--src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index a36c849779..466f08a21f 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -17,6 +17,8 @@ chip soc/intel/alderlake
# DPTF enable
register "dptf_enable" = "1"
+ register "tcc_offset" = "10" # TCC of 90
+
# Enable CNVi BT
register "CnviBtCore" = "true"