diff options
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 647ea42ffe..b6b49dc361 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,6 +3,16 @@ chip soc/intel/alderlake device lapic 0 on end end + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2 @@ -90,6 +100,14 @@ chip soc/intel/alderlake device generic 0 on end end end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end device ref heci1 on end device ref sata on end device ref pcie_rp5 on |