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-rw-r--r--src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index eb85cb5323..d19f627393 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -83,14 +83,12 @@ chip soc/intel/alderlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
- #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI1 | Fingerprint MCU |
#| I2C0 | Audio |
#| I2C3 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#+-------------------+---------------------------+
- register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,