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-rw-r--r--src/mainboard/google/auron_paine/Kconfig65
-rw-r--r--src/mainboard/google/auron_paine/Kconfig.name2
-rw-r--r--src/mainboard/google/auron_paine/Makefile.inc27
-rw-r--r--src/mainboard/google/auron_paine/acpi/ec.asl20
-rw-r--r--src/mainboard/google/auron_paine/acpi/haswell_pci_irqs.asl82
-rw-r--r--src/mainboard/google/auron_paine/acpi/mainboard.asl118
-rw-r--r--src/mainboard/google/auron_paine/acpi/platform.asl82
-rw-r--r--src/mainboard/google/auron_paine/acpi/superio.asl25
-rw-r--r--src/mainboard/google/auron_paine/acpi/thermal.asl201
-rw-r--r--src/mainboard/google/auron_paine/acpi/video.asl38
-rw-r--r--src/mainboard/google/auron_paine/acpi_tables.c66
-rw-r--r--src/mainboard/google/auron_paine/board_info.txt6
-rw-r--r--src/mainboard/google/auron_paine/chromeos.c53
-rw-r--r--src/mainboard/google/auron_paine/chromeos.fmd38
-rw-r--r--src/mainboard/google/auron_paine/cmos.layout110
-rw-r--r--src/mainboard/google/auron_paine/devicetree.cb108
-rw-r--r--src/mainboard/google/auron_paine/dsdt.asl57
-rw-r--r--src/mainboard/google/auron_paine/ec.c49
-rw-r--r--src/mainboard/google/auron_paine/ec.h58
-rw-r--r--src/mainboard/google/auron_paine/fadt.c47
-rw-r--r--src/mainboard/google/auron_paine/gpio.h120
-rw-r--r--src/mainboard/google/auron_paine/hda_verb.c119
-rw-r--r--src/mainboard/google/auron_paine/mainboard.c73
-rw-r--r--src/mainboard/google/auron_paine/onboard.h26
-rw-r--r--src/mainboard/google/auron_paine/pei_data.c63
-rw-r--r--src/mainboard/google/auron_paine/romstage.c48
-rw-r--r--src/mainboard/google/auron_paine/smihandler.c134
-rw-r--r--src/mainboard/google/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.xxd16
-rw-r--r--src/mainboard/google/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.xxd16
-rw-r--r--src/mainboard/google/auron_paine/spd/Makefile.inc53
-rw-r--r--src/mainboard/google/auron_paine/spd/Micron_4KTF25664HZ.spd.xxd16
-rw-r--r--src/mainboard/google/auron_paine/spd/empty.spd.xxd16
-rw-r--r--src/mainboard/google/auron_paine/spd/spd.c132
-rw-r--r--src/mainboard/google/auron_paine/spd/spd.h39
-rw-r--r--src/mainboard/google/auron_paine/thermal.h35
35 files changed, 0 insertions, 2158 deletions
diff --git a/src/mainboard/google/auron_paine/Kconfig b/src/mainboard/google/auron_paine/Kconfig
deleted file mode 100644
index 147f37d883..0000000000
--- a/src/mainboard/google/auron_paine/Kconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-if BOARD_GOOGLE_AURON_PAINE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select SOC_INTEL_BROADWELL
- select BOARD_ROMSIZE_KB_8192
- select EC_GOOGLE_CHROMEEC
- select HAVE_ACPI_TABLES
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_RESUME
- select HAVE_SMI_HANDLER
- select MAINBOARD_HAS_CHROMEOS
- select MAINBOARD_HAS_LPC_TPM
- select INTEL_INT15
-
-config CHROMEOS
- select EC_GOOGLE_CHROMEEC_SWITCHES
- select EC_SOFTWARE_SYNC
- select CHROMEOS_RAMOOPS_DYNAMIC
- select LID_SWITCH
- select VBOOT_VBNV_CMOS
- select VIRTUAL_DEV_SWITCH
-
-config VBOOT_RAMSTAGE_INDEX
- hex
- default 0x2
-
-config VBOOT_REFCODE_INDEX
- hex
- default 0x3
-
-config MAINBOARD_DIR
- string
- default google/auron_paine
-
-config MAINBOARD_PART_NUMBER
- string
- default "Auron Paine"
-
-config IRQ_SLOT_COUNT
- int
- default 18
-
-config MAX_CPUS
- int
- default 8
-
-config VGA_BIOS_FILE
- string
- default "pci8086,0166.rom"
-
-config HAVE_IFD_BIN
- bool
- default n
-
-config HAVE_ME_BIN
- bool
- default n
-
-
-config MAINBOARD_FAMILY
- string
- depends on GENERATE_SMBIOS_TABLES
- default "Google_Auron"
-endif
diff --git a/src/mainboard/google/auron_paine/Kconfig.name b/src/mainboard/google/auron_paine/Kconfig.name
deleted file mode 100644
index 664315def8..0000000000
--- a/src/mainboard/google/auron_paine/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_AURON_PAINE
- bool "Auron_Paine"
diff --git a/src/mainboard/google/auron_paine/Makefile.inc b/src/mainboard/google/auron_paine/Makefile.inc
deleted file mode 100644
index c54c85e765..0000000000
--- a/src/mainboard/google/auron_paine/Makefile.inc
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2014 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-subdirs-y += spd
-
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-romstage-y += pei_data.c
-ramstage-y += pei_data.c
diff --git a/src/mainboard/google/auron_paine/acpi/ec.asl b/src/mainboard/google/auron_paine/acpi/ec.asl
deleted file mode 100644
index f7c8e273fb..0000000000
--- a/src/mainboard/google/auron_paine/acpi/ec.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include <mainboard/google/auron_paine/ec.h>
-
-/* ACPI code for EC functions */
-#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/auron_paine/acpi/haswell_pci_irqs.asl b/src/mainboard/google/auron_paine/acpi/haswell_pci_irqs.asl
deleted file mode 100644
index 40658a9839..0000000000
--- a/src/mainboard/google/auron_paine/acpi/haswell_pci_irqs.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This is board specific information: IRQ routing for IvyBridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // Mini-HD Audio 0:3.0
- Package() { 0x0003ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // EHCI 0:1d.0
- Package() { 0x001dffff, 0, 0, 19 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, 0, 18 },
- // LPC devices 0:1f.0
- Package() { 0x001fffff, 0, 0, 22 },
- Package() { 0x001fffff, 1, 0, 18 },
- Package() { 0x001fffff, 2, 0, 17 },
- Package() { 0x001fffff, 3, 0, 16 },
- // Serial IO 0:15.0
- Package() { 0x0015ffff, 0, 0, 20 },
- Package() { 0x0015ffff, 1, 0, 21 },
- Package() { 0x0015ffff, 2, 0, 21 },
- Package() { 0x0015ffff, 3, 0, 21 },
- // SDIO 0:17.0
- Package() { 0x0017ffff, 0, 0, 23 },
- })
- } Else {
- Return (Package() {
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Mini-HD Audio 0:3.0
- Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- // XHCI 0:14.0
- Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // Serial IO 0:15.0
- Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
- Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
- // SDIO 0:17.0
- Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- })
- }
-}
diff --git a/src/mainboard/google/auron_paine/acpi/mainboard.asl b/src/mainboard/google/auron_paine/acpi/mainboard.asl
deleted file mode 100644
index fe68e3015b..0000000000
--- a/src/mainboard/google/auron_paine/acpi/mainboard.asl
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <mainboard/google/auron_paine/onboard.h>
-
-Scope (\_SB)
-{
- Device (LID0)
- {
- Name(_HID, EisaId("PNP0C0D"))
- Method(_LID, 0)
- {
- Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
- Return (\LIDS)
- }
-
-
- // There is no GPIO for LID, the EC pulses WAKE# pin instead.
- // There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
- Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
- }
-
- Device (PWRB)
- {
- Name(_HID, EisaId("PNP0C0C"))
- }
-}
-
-/*
- * LPC Trusted Platform Module
- */
-Scope (\_SB.PCI0.LPCB)
- {
- #include <drivers/pc80/tpm/acpi/tpm.asl>
-}
-
-Scope (\_SB.PCI0.I2C0)
-{
- Device (ETPA)
- {
- Name (_HID, "ELAN0000")
- Name (_DDN, "Elan Touchpad")
- Name (_UID, 1)
- Name (ISTP, 1) /* Touchpad */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x15, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C0", // ResourceSource
- )
- Interrupt (ResourceConsumer, Edge, ActiveLow)
- {
- BOARD_TRACKPAD_IRQ
- }
- })
-
- Method (_STA)
- {
- If (LEqual (\S1EN, 1)) {
- Return (0xF)
- } Else {
- Return (0x0)
- }
- }
-
- Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (Local0)
- }
- }
-
- /* Allow device to power off in S0 */
- Name (_S0W, 4)
- }
-}
-
-Scope (\_SB.PCI0.RP01)
-{
- Device (WLAN)
- {
- Name (_ADR, 0x00000000)
-
- /* GPIO10 is WLAN_WAKE_L_Q */
- Name (GPIO, 10)
-
- Name (_PRW, Package() { GPIO, 3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO)
- }
- }
- }
-}
diff --git a/src/mainboard/google/auron_paine/acpi/platform.asl b/src/mainboard/google/auron_paine/acpi/platform.asl
deleted file mode 100644
index 1bd054da06..0000000000
--- a/src/mainboard/google/auron_paine/acpi/platform.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
- APMC, 8, // APM command
- APMS, 8 // APM status
-}
-
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
- DBG0, 8
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
- Store (Arg0, SMIF) // SMI Function
- Store (0, TRP0) // Generate trap
- Return (SMIF) // Return value of SMI handler
-}
-
-/* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
-Method(_PIC, 1)
-{
- // Remember the OS' IRQ routing choice.
- Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
- /* Update AC status */
- Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
- if (LNotEqual (Local0, \PWRS)) {
- Store (Local0, \PWRS)
- Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
- }
-
- /* Update LID status */
- Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
- if (LNotEqual (Local0, \LIDS)) {
- Store (Local0, \LIDS)
- Notify (\_SB.LID0, 0x80)
- }
-
- Return(Package(){0,0})
-}
diff --git a/src/mainboard/google/auron_paine/acpi/superio.asl b/src/mainboard/google/auron_paine/acpi/superio.asl
deleted file mode 100644
index 07d6b23e53..0000000000
--- a/src/mainboard/google/auron_paine/acpi/superio.asl
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include <mainboard/google/auron_paine/ec.h>
-
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
-#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
-#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
-
-/* ACPI code for EC SuperIO functions */
-#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/auron_paine/acpi/thermal.asl b/src/mainboard/google/auron_paine/acpi/thermal.asl
deleted file mode 100644
index 2221abc3a7..0000000000
--- a/src/mainboard/google/auron_paine/acpi/thermal.asl
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <mainboard/google/auron_paine/thermal.h>
-
-// Thermal Zone
-
-Scope (\_TZ)
-{
- ThermalZone (THRM)
- {
- Name (_TC1, 0x02)
- Name (_TC2, 0x05)
-
- // Thermal zone polling frequency: 10 seconds
- Name (_TZP, 100)
-
- // Thermal sampling period for passive cooling: 2 seconds
- Name (_TSP, 20)
-
- // Convert from Degrees C to 1/10 Kelvin for ACPI
- Method (CTOK, 1) {
- // 10th of Degrees C
- Multiply (Arg0, 10, Local0)
-
- // Convert to Kelvin
- Add (Local0, 2732, Local0)
-
- Return (Local0)
- }
-
- // Threshold for OS to shutdown
- Method (_CRT, 0, Serialized)
- {
- Return (CTOK (\TCRT))
- }
-
- // Threshold for passive cooling
- Method (_PSV, 0, Serialized)
- {
- Return (CTOK (\TPSV))
- }
-
- // Processors used for passive cooling
- Method (_PSL, 0, Serialized)
- {
- Return (\PPKG ())
- }
-
- Method (TCHK, 0, Serialized)
- {
- // Get Temperature from TIN# set in NVS
- Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0)
-
- // Check for sensor not calibrated
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) {
- Return (CTOK(0))
- }
-
- // Check for sensor not present
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
- Return (CTOK(0))
- }
-
- // Check for sensor not powered
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
- Return (CTOK(0))
- }
-
- // Check for sensor bad reading
- If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
- Return (CTOK(0))
- }
-
- // Adjust by offset to get Kelvin
- Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
-
- // Convert to 1/10 Kelvin
- Multiply (Local0, 10, Local0)
- Return (Local0)
- }
-
- Method (_TMP, 0, Serialized)
- {
- // Get temperature from EC in deci-kelvin
- Store (TCHK (), Local0)
-
- // Critical temperature in deci-kelvin
- Store (CTOK (\TCRT), Local1)
-
- If (LGreaterEqual (Local0, Local1)) {
- Store ("CRITICAL TEMPERATURE", Debug)
- Store (Local0, Debug)
-
- // Wait 1 second for EC to re-poll
- Sleep (1000)
-
- // Re-read temperature from EC
- Store (TCHK (), Local0)
-
- Store ("RE-READ TEMPERATURE", Debug)
- Store (Local0, Debug)
- }
-
- Return (Local0)
- }
-
- /* CTDP Down */
- Method (_AC0) {
- If (LLessEqual (\FLVL, 0)) {
- Return (CTOK (CTL_TDP_THRESHOLD_OFF))
- } Else {
- Return (CTOK (CTL_TDP_THRESHOLD_ON))
- }
- }
-
- /* CTDP Nominal */
- Method (_AC1) {
- If (LLessEqual (\FLVL, 1)) {
- Return (CTOK (CTL_TDP_THRESHILD_NORMAL))
- } Else {
- Return (CTOK (CTL_TDP_THRESHILD_NORMAL))
- }
- }
-
- Name (_AL0, Package () { TDP0 })
- Name (_AL1, Package () { TDP1 })
-
- PowerResource (TNP0, 0, 0)
- {
- Method (_STA) {
- If (LLessEqual (\FLVL, 0)) {
- Return (One)
- } Else {
- Return (Zero)
- }
- }
- Method (_ON) {
- Store (0, \FLVL)
-
- /* Enable Power Limit */
- \_SB.PCI0.MCHC.CTLE (CTL_TDP_POWER_LIMIT)
-
- Notify (\_TZ.THRM, 0x81)
- }
- Method (_OFF) {
- Store (1, \FLVL)
-
- /* Disable Power Limit */
- \_SB.PCI0.MCHC.CTLD ()
-
- Notify (\_TZ.THRM, 0x81)
- }
- }
-
- PowerResource (TNP1, 0, 0)
- {
- Method (_STA) {
- If (LLessEqual (\FLVL, 1)) {
- Return (One)
- } Else {
- Return (Zero)
- }
- }
- Method (_ON) {
- Store (1, \FLVL)
- Notify (\_TZ.THRM, 0x81)
- }
- Method (_OFF) {
- Store (1, \FLVL)
- Notify (\_TZ.THRM, 0x81)
- }
- }
-
- Device (TDP0)
- {
- Name (_HID, EISAID ("PNP0C0B"))
- Name (_UID, 0)
- Name (_PR0, Package () { TNP0 })
- }
-
- Device (TDP1)
- {
- Name (_HID, EISAID ("PNP0C0B"))
- Name (_UID, 1)
- Name (_PR0, Package () { TNP1 })
- }
- }
-}
diff --git a/src/mainboard/google/auron_paine/acpi/video.asl b/src/mainboard/google/auron_paine/acpi/video.asl
deleted file mode 100644
index 68946552a6..0000000000
--- a/src/mainboard/google/auron_paine/acpi/video.asl
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// Brightness write
-Method (BRTW, 1, Serialized)
-{
- // TODO
-}
-
-// Hot Key Display Switch
-Method (HKDS, 1, Serialized)
-{
- // TODO
-}
-
-// Lid Switch Display Switch
-Method (LSDS, 1, Serialized)
-{
- // TODO
-}
-
-// Brightness Notification
-Method(BRTN,1,Serialized)
-{
- // TODO (no displays defined yet)
-}
diff --git a/src/mainboard/google/auron_paine/acpi_tables.c b/src/mainboard/google/auron_paine/acpi_tables.c
deleted file mode 100644
index f6fc3fdbbf..0000000000
--- a/src/mainboard/google/auron_paine/acpi_tables.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <soc/acpi.h>
-#include <soc/nvs.h>
-#include "thermal.h"
-
-const unsigned char *AmlCode;
-
-static void acpi_update_thermal_table(global_nvs_t *gnvs)
-{
- gnvs->tmps = CTL_TDP_SENSOR_ID;
-
- gnvs->tcrt = CRITICAL_TEMPERATURE;
- gnvs->tpsv = PASSIVE_TEMPERATURE;
- gnvs->tmax = MAX_TEMPERATURE;
- gnvs->flvl = 1;
-}
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
- acpi_init_gnvs(gnvs);
-
- /* Enable USB ports in S3 */
- gnvs->s3u0 = 1;
-
- /* Disable USB ports in S5 */
- gnvs->s5u0 = 0;
-
- acpi_update_thermal_table(gnvs);
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- return acpi_madt_irq_overrides(current);
-}
diff --git a/src/mainboard/google/auron_paine/board_info.txt b/src/mainboard/google/auron_paine/board_info.txt
deleted file mode 100644
index 2c6971b31e..0000000000
--- a/src/mainboard/google/auron_paine/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Auron Paine Broadwell chromebook
-Category: laptop
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/auron_paine/chromeos.c b/src/mainboard/google/auron_paine/chromeos.c
deleted file mode 100644
index 61b3e4ef1e..0000000000
--- a/src/mainboard/google/auron_paine/chromeos.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/gpio.h>
-
-/* SPI Write protect is GPIO 16 */
-#define CROS_WP_GPIO 58
-
-#ifndef __PRE_RAM__
-#include <boot/coreboot_tables.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"},
- {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
- {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
- {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- {-1, ACTIVE_HIGH, 0, "power"},
- {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-#endif
-
-int get_write_protect_state(void)
-{
- return get_gpio(CROS_WP_GPIO);
-}
-
-static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
-};
-
-void mainboard_chromeos_acpi_generate(void)
-{
- chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
-}
diff --git a/src/mainboard/google/auron_paine/chromeos.fmd b/src/mainboard/google/auron_paine/chromeos.fmd
deleted file mode 100644
index 113fba6e6f..0000000000
--- a/src/mainboard/google/auron_paine/chromeos.fmd
+++ /dev/null
@@ -1,38 +0,0 @@
-FLASH@0xff800000 0x800000 {
- SI_ALL@0x0 0x200000 {
- SI_DESC@0x0 0x1000
- SI_ME@0x1000 0x1ff000
- }
- SI_BIOS@0x200000 0x600000 {
- RW_SECTION_A@0x0 0xf0000 {
- VBLOCK_A@0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0xdffc0
- RW_FWID_A@0xeffc0 0x40
- }
- RW_SECTION_B@0xf0000 0xf0000 {
- VBLOCK_B@0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0xdffc0
- RW_FWID_B@0xeffc0 0x40
- }
- RW_MRC_CACHE@0x1e0000 0x10000
- RW_ELOG@0x1f0000 0x4000
- RW_SHARED@0x1f4000 0x4000 {
- SHARED_DATA@0x0 0x2000
- VBLOCK_DEV@0x2000 0x2000
- }
- RW_VPD@0x1f8000 0x2000
- RW_UNUSED@0x1fa000 0x6000
- RW_LEGACY(CBFS)@0x200000 0x200000
- WP_RO@0x400000 0x200000 {
- RO_VPD@0x0 0x4000
- RO_UNUSED@0x4000 0xc000
- RO_SECTION@0x10000 0x1f0000 {
- FMAP@0x0 0x800
- RO_FRID@0x800 0x40
- RO_FRID_PAD@0x840 0x7c0
- GBB@0x1000 0xef000
- COREBOOT(CBFS)@0xf0000 0x100000
- }
- }
- }
-}
diff --git a/src/mainboard/google/auron_paine/cmos.layout b/src/mainboard/google/auron_paine/cmos.layout
deleted file mode 100644
index b575e02970..0000000000
--- a/src/mainboard/google/auron_paine/cmos.layout
+++ /dev/null
@@ -1,110 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96 4 r 0 status_c_rsvd
-#100 1 r 0 uf_flag
-#101 1 r 0 af_flag
-#102 1 r 0 pf_flag
-#103 1 r 0 irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104 7 r 0 status_d_rsvd
-#111 1 r 0 valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112 8 r 0 diag_rsvd1
-
-# -----------------------------------------------------------------
-0 120 r 0 reserved_memory
-#120 264 r 0 unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#390 2 r 0 unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-392 3 e 5 baud_rate
-395 4 e 6 debug_level
-#399 1 r 0 unused
-
-# coreboot config options: cpu
-400 1 e 2 hyper_threading
-#401 7 r 0 unused
-
-# coreboot config options: southbridge
-408 1 e 1 nmi
-409 2 e 7 power_on_after_fail
-#411 5 r 0 unused
-
-# coreboot config options: bootloader
-#Used by ChromeOS:
-416 128 r 0 vbnv
-#544 440 r 0 unused
-
-# SandyBridge MRC Scrambler Seed values
-896 32 r 0 mrc_scrambler_seed
-928 32 r 0 mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984 16 h 0 check_sum
-#1000 24 r 0 amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 1 Emergency
-6 2 Alert
-6 3 Critical
-6 4 Error
-6 5 Warning
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Disable
-7 1 Enable
-7 2 Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/google/auron_paine/devicetree.cb b/src/mainboard/google/auron_paine/devicetree.cb
deleted file mode 100644
index 5872cf293c..0000000000
--- a/src/mainboard/google/auron_paine/devicetree.cb
+++ /dev/null
@@ -1,108 +0,0 @@
-chip soc/intel/broadwell
-
- # Enable eDP Hotplug with 6ms pulse
- register "gpu_dp_d_hotplug" = "0x06"
-
- # Disable DisplayPort C Hotplug
- register "gpu_dp_c_hotplug" = "0x00"
-
- # Enable HDMI Hotplug with 6ms pulse
- register "gpu_dp_b_hotplug" = "0x06"
-
- # Set backlight PWM values for eDP
- register "gpu_cpu_backlight" = "0x00000200"
- register "gpu_pch_backlight" = "0x04000000"
-
- # Enable Panel and configure power delays
- register "gpu_panel_port_select" = "1" # eDP
- register "gpu_panel_power_cycle_delay" = "5" # 400ms
- register "gpu_panel_power_up_delay" = "400" # 40ms
- register "gpu_panel_power_down_delay" = "150" # 15ms
- register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
- register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
-
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
- # EC range is 0x800-0x9ff
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x00fc0901"
-
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
- register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
- register "gpe0_en_3" = "0x00000000"
- register "gpe0_en_4" = "0x00000000"
-
- register "sata_port_map" = "0x1"
- register "sio_acpi_mode" = "1"
-
- # DTLE DATA / EDGE values
- register "sata_port0_gen3_dtle" = "0x5"
- register "sata_port1_gen3_dtle" = "0x5"
-
- # Force enable ASPM for PCIe Port1
- register "pcie_port_force_aspm" = "0x01"
-
- # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
- register "icc_clock_disable" = "0x013c0000"
-
- register "s0ix_enable" = "1"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
-
- device domain 0 on
- device pci 00.0 on end # host bridge
- device pci 02.0 on end # vga controller
- device pci 03.0 on end # mini-hd audio
- device pci 13.0 off end # Smart Sound Audio DSP
- device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
- device pci 15.3 off end # GSPI0
- device pci 15.4 off end # GSPI1
- device pci 15.5 off end # UART0
- device pci 15.6 off end # UART1
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 17.0 off end # SDIO
- device pci 19.0 off end # GbE
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 off end # PCIe Port #3
- device pci 1c.3 off end # PCIe Port #4
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1d.0 on end # USB2 EHCI
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on
- chip drivers/pc80/tpm
- # Rising edge interrupt
- register "irq_polarity" = "2"
- device pnp 0c31.0 on
- irq 0x70 = 10
- end
- end
- chip ec/google/chromeec
- device pnp 0c09.0 on end
- end
- end # LPC bridge
- device pci 1f.2 on end # SATA Controller
- device pci 1f.3 off end # SMBus
- device pci 1f.6 on end # Thermal
- end
-end
diff --git a/src/mainboard/google/auron_paine/dsdt.asl b/src/mainboard/google/auron_paine/dsdt.asl
deleted file mode 100644
index 531d6a7247..0000000000
--- a/src/mainboard/google/auron_paine/dsdt.asl
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x02, // DSDT revision: ACPI v2.0
- "COREv4", // OEM id
- "COREBOOT", // OEM table id
- 0x20110725 // OEM revision
-)
-{
- // Some generic macros
- #include <soc/intel/broadwell/acpi/platform.asl>
-
- // global NVS and variables
- #include <soc/intel/broadwell/acpi/globalnvs.asl>
-
- // General Purpose Events
- //#include "acpi/gpe.asl"
-
- // CPU
- #include <soc/intel/broadwell/acpi/cpu.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <soc/intel/broadwell/acpi/systemagent.asl>
- #include <soc/intel/broadwell/acpi/pch.asl>
- }
- }
-
- // Thermal handler
- #include "acpi/thermal.asl"
-
- // Chrome OS specific
- #include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
- // Chipset specific sleep states
- #include <soc/intel/broadwell/acpi/sleepstates.asl>
-
- // Mainboard specific
- #include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/google/auron_paine/ec.c b/src/mainboard/google/auron_paine/ec.c
deleted file mode 100644
index 5feafb8d08..0000000000
--- a/src/mainboard/google/auron_paine/ec.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <types.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include "ec.h"
-
-void mainboard_ec_init(void)
-{
- printk(BIOS_DEBUG, "mainboard_ec_init\n");
- post_code(0xf0);
-
- /* Restore SCI event mask on resume. */
- if (acpi_is_wakeup_s3()) {
- google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
- MAINBOARD_EC_S3_WAKE_EVENTS);
-
- /* Disable SMI and wake events */
- google_chromeec_set_smi_mask(0);
-
- /* Clear pending events */
- while (google_chromeec_get_event() != 0)
- ;
- google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
- } else {
- google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
- MAINBOARD_EC_S5_WAKE_EVENTS);
- }
-
- /* Clear wake events, these are enabled on entry to sleep */
- google_chromeec_set_wake_mask(0);
-
- post_code(0xf1);
-}
diff --git a/src/mainboard/google/auron_paine/ec.h b/src/mainboard/google/auron_paine/ec.h
deleted file mode 100644
index 9bfb5557a4..0000000000
--- a/src/mainboard/google/auron_paine/ec.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_EC_H
-#define MAINBOARD_EC_H
-
-#include <ec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-
-#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */
-#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
-
-#define MAINBOARD_EC_SCI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
-
-#define MAINBOARD_EC_SMI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
-
-/* EC can wake from S5 with lid or power button */
-#define MAINBOARD_EC_S5_WAKE_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/* EC can wake from S3 with lid or power button or key press */
-#define MAINBOARD_EC_S3_WAKE_EVENTS \
- (MAINBOARD_EC_S5_WAKE_EVENTS |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
-
-/* Log EC wake events plus EC shutdown events */
-#define MAINBOARD_EC_LOG_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
-
-#endif
diff --git a/src/mainboard/google/auron_paine/fadt.c b/src/mainboard/google/auron_paine/fadt.c
deleted file mode 100644
index 570689b018..0000000000
--- a/src/mainboard/google/auron_paine/fadt.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <soc/acpi.h>
-
-void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
-
- memset((void *) fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = sizeof(acpi_fadt_t);
- header->revision = 5;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 1;
-
- fadt->firmware_ctrl = (unsigned long) facs;
- fadt->dsdt = (unsigned long) dsdt;
- fadt->model = 1;
- fadt->preferred_pm_profile = PM_MOBILE;
-
- fadt->x_firmware_ctl_l = (unsigned long)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (unsigned long)dsdt;
- fadt->x_dsdt_h = 0;
-
- acpi_fill_in_fadt(fadt);
-
- header->checksum =
- acpi_checksum((void *) fadt, header->length);
-}
diff --git a/src/mainboard/google/auron_paine/gpio.h b/src/mainboard/google/auron_paine/gpio.h
deleted file mode 100644
index 667f977808..0000000000
--- a/src/mainboard/google/auron_paine/gpio.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef AURON_PAINE_GPIO_H
-#define AURON_PAINE_GPIO_H
-
-#include <soc/gpio.h>
-
-static const struct gpio_config mainboard_gpio_config[] = {
- PCH_GPIO_UNUSED, /* 0: UNUSED */
- PCH_GPIO_UNUSED, /* 1: UNUSED */
- PCH_GPIO_UNUSED, /* 2: UNUSED */
- PCH_GPIO_UNUSED, /* 3: UNUSED */
- PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
- PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
- PCH_GPIO_UNUSED, /* 6: UNUSED */
- PCH_GPIO_UNUSED, /* 7: UNUSED */
- PCH_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */
- PCH_GPIO_INPUT, /* 9: RAM_ID1 */
- PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
- PCH_GPIO_UNUSED, /* 11: UNUSED */
- PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
- PCH_GPIO_INPUT, /* 13: RAM_ID0 */
- PCH_GPIO_INPUT, /* 14: EC_IN_RW */
- PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
- PCH_GPIO_UNUSED, /* 16: UNUSED */
- PCH_GPIO_UNUSED, /* 17: UNUSED */
- PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
- PCH_GPIO_UNUSED, /* 19: UNUSED */
- PCH_GPIO_UNUSED, /* 20: UNUSED */
- PCH_GPIO_UNUSED, /* 21: UNUSED */
- PCH_GPIO_UNUSED, /* 22: UNUSED */
- PCH_GPIO_UNUSED, /* 23: UNUSED */
- PCH_GPIO_UNUSED, /* 24: UNUSED */
- PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
- PCH_GPIO_UNUSED, /* 26: UNUSED */
- PCH_GPIO_UNUSED, /* 27: UNUSED */
- PCH_GPIO_UNUSED, /* 28: UNUSED */
- PCH_GPIO_UNUSED, /* 29: UNUSED */
- PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
- PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
- PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
- PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
- PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
- PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
- PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
- PCH_GPIO_UNUSED, /* 37: UNUSED */
- PCH_GPIO_UNUSED, /* 38: UNUSED */
- PCH_GPIO_UNUSED, /* 39: UNUSED */
- PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
- PCH_GPIO_UNUSED, /* 41: UNUSED */
- PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
- PCH_GPIO_UNUSED, /* 43: UNUSED */
- PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
- PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
- PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
- PCH_GPIO_INPUT, /* 47: RAM_ID2 */
- PCH_GPIO_UNUSED, /* 48: UNUSED */
- PCH_GPIO_UNUSED, /* 49: UNUSED */
- PCH_GPIO_UNUSED, /* 50: UNUSED */
- PCH_GPIO_INPUT, /* 51: ALS_INT_L */
- PCH_GPIO_INPUT, /* 52: SIM_DET */
- PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
- PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
- PCH_GPIO_UNUSED, /* 55: UNUSED */
- PCH_GPIO_UNUSED, /* 56: UNUSED */
- PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
- PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
- PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
- PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
- PCH_GPIO_UNUSED, /* 61: UNUSED */
- PCH_GPIO_UNUSED, /* 62: UNUSED */
- PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
- PCH_GPIO_UNUSED, /* 64: UNUSED */
- PCH_GPIO_UNUSED, /* 65: UNUSED */
- PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
- PCH_GPIO_UNUSED, /* 67: UNUSED */
- PCH_GPIO_UNUSED, /* 68: UNUSED */
- PCH_GPIO_UNUSED, /* 69: UNUSED */
- PCH_GPIO_UNUSED, /* 70: UNUSED */
- PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
- PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
- PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
- PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
- PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
- PCH_GPIO_UNUSED, /* 76: UNUSED */
- PCH_GPIO_UNUSED, /* 77: UNUSED */
- PCH_GPIO_UNUSED, /* 78: UNUSED */
- PCH_GPIO_UNUSED, /* 79: UNUSED */
- PCH_GPIO_UNUSED, /* 80: UNUSED */
- PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
- PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
- PCH_GPIO_UNUSED, /* 83: UNUSED */
- PCH_GPIO_UNUSED, /* 84: UNUSED */
- PCH_GPIO_UNUSED, /* 85: UNUSED */
- PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
- PCH_GPIO_UNUSED, /* 87: UNUSED */
- PCH_GPIO_UNUSED, /* 88: UNUSED */
- PCH_GPIO_UNUSED, /* 89: UNUSED */
- PCH_GPIO_UNUSED, /* 90: UNUSED */
- PCH_GPIO_UNUSED, /* 91: UNUSED */
- PCH_GPIO_UNUSED, /* 92: UNUSED */
- PCH_GPIO_UNUSED, /* 93: UNUSED */
- PCH_GPIO_UNUSED, /* 94: UNUSED */
- PCH_GPIO_END
-};
-
-#endif
diff --git a/src/mainboard/google/auron_paine/hda_verb.c b/src/mainboard/google/auron_paine/hda_verb.c
deleted file mode 100644
index 4ee9c09afe..0000000000
--- a/src/mainboard/google/auron_paine/hda_verb.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- /* coreboot specific header */
- 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
- 0x10ec0283, // Subsystem ID
- 0x0000000d, // Number of jacks (NID entries)
-
- 0x0017ff00, // Function Reset
- 0x0017ff00, // Double Function Reset
- 0x000F0000, // Pad - get vendor id
- 0x000F0002, // Pad - get revision id
-
- /* Bits 31:28 - Codec Address */
- /* Bits 27:20 - NID */
- /* Bits 19:8 - Verb ID */
- /* Bits 7:0 - Payload */
-
- /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */
- 0x00172083,
- 0x00172102,
- 0x001722ec,
- 0x00172310,
-
- /* Pin Widget Verb Table */
-
- /* Pin Complex (NID 0x12) DMIC - Disabled */
- 0x01271cf0, //
- 0x01271d11, //
- 0x01271e11, //
- 0x01271f41, //
-
- /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
- 0x01471c10, // group 1, cap 0
- 0x01471d01, // no connector, no jack detect
- 0x01471e17, // speaker out, analog
- 0x01471f90, // fixed function, internal, Location N/A
-
- /* Pin Complex (NID 0x17) MONO Out - Disabled */
- 0x01771cf0, //
- 0x01771d11, //
- 0x01771e11, //
- 0x01771f41, //
-
- /* Pin Complex (NID 0x18) Disabled */
- 0x01871cf0, //
- 0x01871d11, //
- 0x01871e11, //
- 0x01871f41, //
-
- /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
- 0x01971c20, // group2, cap 0
- 0x01971d10, // black, jack detect
- 0x01971ea1, // Mic in, 3.5mm Jack
- 0x01971f03, // connector, External left panel
-
- /* Pin Complex (NID 0x1A) LINE1 - Internal Mic */
- 0x01a71c11, // group 1, cap 1
- 0x01a71d01, // no connector, no jack detect
- 0x01a71ea7, // mic in, analog connection
- 0x01a71f90, // Fixed function, internal, Location N/A
-
- /* Pin Complex (NID 0x1B) LINE2 - Disabled */
- 0x01b71cf0, //
- 0x01b71d11, //
- 0x01b71e11, //
- 0x01b71f41, //
-
- /* Pin Complex (NID 0x1D) PCBeep */
- 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
- 0x01d71d81, // mute spkr on hpout
- 0x01d71e15, // pcbeep en able, checksum
- 0x01d71f40, // no physical, Internal, Location N/A
-
- /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
- 0x01e71cf0, //
- 0x01e71d11, //
- 0x01e71e11, //
- 0x01e71f41, //
-
- /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
- 0x02171c21, // group2, cap 1
- 0x02171d10, // black, jack detect
- 0x02171e21, // HPOut, 3.5mm Jack
- 0x02171f03, // connector, left panel
-
- /* Undocumented settings from Realtek (needed for beep_gen) */
- /* Widget node 0x20 */
- 0x02050010,
- 0x02040c20,
- 0x0205001b,
- 0x0204081b,
-};
-
-const u32 pc_beep_verbs[] = {
- 0x00170500, /* power up everything (codec, dac, adc, mixers) */
- 0x01470740, /* enable speaker out */
- 0x01470c02, /* set speaker EAPD pin */
- 0x0143b01f, /* unmute speaker */
- 0x00c37100, /* unmute mixer nid 0xc input 1 */
- 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
-};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/auron_paine/mainboard.c b/src/mainboard/google/auron_paine/mainboard.c
deleted file mode 100644
index 81ca9cf1bc..0000000000
--- a/src/mainboard/google/auron_paine/mainboard.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <smbios.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <drivers/intel/gma/int15.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include "ec.h"
-#include "onboard.h"
-
-
-static void mainboard_init(device_t dev)
-{
- mainboard_ec_init();
-}
-
-static int mainboard_smbios_data(device_t dev, int *handle,
- unsigned long *current)
-{
- int len = 0;
-
- len += smbios_write_type41(
- current, handle,
- BOARD_TRACKPAD_NAME, /* name */
- BOARD_TRACKPAD_IRQ, /* instance */
- BOARD_TRACKPAD_I2C_BUS, /* segment */
- BOARD_TRACKPAD_I2C_ADDR, /* bus */
- 0, /* device */
- 0); /* function */
-
- return len;
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = mainboard_init;
- dev->ops->get_smbios_data = mainboard_smbios_data;
- dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
- GMA_INT15_PANEL_FIT_CENTERING,
- GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/google/auron_paine/onboard.h b/src/mainboard/google/auron_paine/onboard.h
deleted file mode 100644
index 0314cc73ef..0000000000
--- a/src/mainboard/google/auron_paine/onboard.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef ONBOARD_H
-#define ONBOARD_H
-
-#define BOARD_TRACKPAD_NAME "trackpad"
-#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
-#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
-#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
-#define BOARD_TRACKPAD_I2C_ADDR 0x67
-#define BOARD_TRACKPAD_GEN5_I2C_ADDR 0x24
-
-#endif
diff --git a/src/mainboard/google/auron_paine/pei_data.c b/src/mainboard/google/auron_paine/pei_data.c
deleted file mode 100644
index a5b2384d4c..0000000000
--- a/src/mainboard/google/auron_paine/pei_data.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-
-void mainboard_fill_pei_data(struct pei_data *pei_data)
-{
- pei_data->ec_present = 1;
-
- /* One installed DIMM per channel -- can be changed by SPD init */
- pei_data->dimm_channel0_disabled = 2;
- pei_data->dimm_channel1_disabled = 2;
-
- /* P0: LTE */
- pei_data_usb2_port(pei_data, 0, 0x0150, 1, USB_OC_PIN_SKIP,
- USB_PORT_MINI_PCIE);
- /* P1: POrt A, CN10 */
- pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
- USB_PORT_BACK_PANEL);
- /* P2: CCD */
- pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
- USB_PORT_INTERNAL);
- /* P3: BT */
- pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
- USB_PORT_MINI_PCIE);
- /* P4: Port B, CN6 */
- pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
- USB_PORT_BACK_PANEL);
- /* P5: EMPTY */
- pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
- USB_PORT_SKIP);
- /* P6: SD Card */
- pei_data_usb2_port(pei_data, 6, 0x0150, 1, USB_OC_PIN_SKIP,
- USB_PORT_FLEX);
- /* P7: EMPTY */
- pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
- USB_PORT_SKIP);
-
- /* P1: Port A, CN6 */
- pei_data_usb3_port(pei_data, 0, 1, 0, 0);
- /* P2: EMPTY */
- pei_data_usb3_port(pei_data, 1, 0, USB_OC_PIN_SKIP, 0);
- /* P3: EMPTY */
- pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
- /* P4: EMPTY */
- pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
-}
diff --git a/src/mainboard/google/auron_paine/romstage.c b/src/mainboard/google/auron_paine/romstage.c
deleted file mode 100644
index ce4af5e442..0000000000
--- a/src/mainboard/google/auron_paine/romstage.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbfs.h>
-#include <console/console.h>
-#include <string.h>
-#include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-#include <soc/romstage.h>
-#include <mainboard/google/auron_paine/spd/spd.h>
-#include "gpio.h"
-
-void mainboard_romstage_entry(struct romstage_params *rp)
-{
- struct pei_data pei_data;
-
- post_code(0x32);
-
- /* Ensure the EC is in the right mode for recovery */
- google_chromeec_early_init();
-
- /* Initialize GPIOs */
- init_gpios(mainboard_gpio_config);
-
- /* Fill out PEI DATA */
- memset(&pei_data, 0, sizeof(pei_data));
- mainboard_fill_pei_data(&pei_data);
- mainboard_fill_spd_data(&pei_data);
- rp->pei_data = &pei_data;
-
- /* Call into the real romstage main with this board's attributes. */
- romstage_common(rp);
-}
diff --git a/src/mainboard/google/auron_paine/smihandler.c b/src/mainboard/google/auron_paine/smihandler.c
deleted file mode 100644
index b34a69a451..0000000000
--- a/src/mainboard/google/auron_paine/smihandler.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <soc/pm.h>
-#include <soc/smm.h>
-#include <elog.h>
-#include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
-#include <soc/iomap.h>
-#include <soc/nvs.h>
-#include <soc/pm.h>
-#include <soc/smm.h>
-#include "ec.h"
-
-/* Codec enable: GPIO45 */
-#define GPIO_PP3300_CODEC_EN 45
-/* WLAN / BT enable: GPIO46 */
-#define GPIO_WLAN_DISABLE_L 46
-
-
-static u8 mainboard_smi_ec(void)
-{
- u8 cmd = google_chromeec_get_event();
- u32 pm1_cnt;
-
-#if CONFIG_ELOG_GSMI
- /* Log this event */
- if (cmd)
- elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
-#endif
-
- switch (cmd) {
- case EC_HOST_EVENT_LID_CLOSED:
- printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-
- /* Go to S5 */
- pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
- pm1_cnt |= (0xf << 10);
- outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
- break;
- }
-
- return cmd;
-}
-
-/* gpi_sts is GPIO 47:32 */
-void mainboard_smi_gpi(u32 gpi_sts)
-{
- if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
- /* Process all pending events */
- while (mainboard_smi_ec() != 0)
- ;
- }
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
- /* Disable USB charging if required */
- switch (slp_typ) {
- case ACPI_S3:
- if (smm_get_gnvs()->s3u0 == 0) {
- google_chromeec_set_usb_charge_mode(
- 0, USB_CHARGE_MODE_DISABLED);
- google_chromeec_set_usb_charge_mode(
- 1, USB_CHARGE_MODE_DISABLED);
- }
-
- set_gpio(GPIO_PP3300_CODEC_EN, 0);
-
- /* Enable wake events */
- google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
- break;
- case ACPI_S5:
- if (smm_get_gnvs()->s5u0 == 0) {
- google_chromeec_set_usb_charge_mode(
- 0, USB_CHARGE_MODE_DISABLED);
- google_chromeec_set_usb_charge_mode(
- 1, USB_CHARGE_MODE_DISABLED);
- }
-
- set_gpio(GPIO_PP3300_CODEC_EN, 0);
- set_gpio(GPIO_WLAN_DISABLE_L, 0);
-
- /* Enable wake events */
- google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
- break;
- }
-
- /* Disable SCI and SMI events */
- google_chromeec_set_smi_mask(0);
- google_chromeec_set_sci_mask(0);
-
- /* Clear pending events that may trigger immediate wake */
- while (google_chromeec_get_event() != 0)
- ;
-}
-
-int mainboard_smi_apmc(u8 apmc)
-{
- switch (apmc) {
- case APM_CNT_ACPI_ENABLE:
- google_chromeec_set_smi_mask(0);
- /* Clear all pending events */
- while (google_chromeec_get_event() != 0)
- ;
- google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
- break;
- case APM_CNT_ACPI_DISABLE:
- google_chromeec_set_sci_mask(0);
- /* Clear all pending events */
- while (google_chromeec_get_event() != 0)
- ;
- google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
- break;
- }
- return 0;
-}
diff --git a/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.xxd b/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.xxd
deleted file mode 100644
index 7457006ef4..0000000000
--- a/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.xxd
+++ /dev/null
@@ -1,16 +0,0 @@
-0000000: 92 12 0b 03 04 19 02 02 03 52 01 08 0a 00 fe 00 .........R......
-0000010: 69 78 69 3c 69 11 18 81 20 08 3c 3c 01 40 83 01 ixi<i... .<<.@..
-0000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 62 00 ..............b.
-0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000070: 00 00 00 00 00 80 ad 01 00 00 00 00 00 00 ff ab ................
-0000080: 48 4d 54 34 32 35 53 36 41 46 52 36 41 2d 50 42 HMT425S6AFR6A-PB
-0000090: 20 20 4e 30 80 ad 00 00 00 00 00 00 00 00 00 00 N0............
-00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
diff --git a/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.xxd b/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.xxd
deleted file mode 100644
index f43210615c..0000000000
--- a/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.xxd
+++ /dev/null
@@ -1,16 +0,0 @@
-0000000: 92 13 0b 03 04 19 02 02 03 52 01 08 0a 00 fe 00 .........R......
-0000010: 69 78 69 3c 69 11 18 81 20 08 3c 3c 01 40 83 01 ixi<i... .<<.@..
-0000020: 00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 ................
-0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 62 00 ..............b.
-0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000070: 00 00 00 00 00 80 ad 01 00 00 00 00 00 00 c9 c0 ................
-0000080: 48 4d 54 34 32 35 53 36 43 46 52 36 41 2d 50 42 HMT425S6CFR6A-PB
-0000090: 20 20 4e 30 80 ad 00 00 00 00 00 00 00 00 00 00 N0............
-00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
diff --git a/src/mainboard/google/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron_paine/spd/Makefile.inc
deleted file mode 100644
index ae790c12ec..0000000000
--- a/src/mainboard/google/auron_paine/spd/Makefile.inc
+++ /dev/null
@@ -1,53 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2014 Google Inc.
-## Copyright (C) 2015 CrowdStrike Inc. <georg@crowdstrike.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-romstage-y += spd.c
-
-SPD_BIN = $(obj)/spd.bin
-
-# { GPIO47, GPIO9, GPIO13 }
-SPD_SOURCES = Micron_4KTF25664HZ # 0b0000
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001
-# ^ Hynix HMT425S6AFR6A-PBA
-SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0010
-# ^ Hynix HMT425S6CFR6A-PBA
-SPD_SOURCES += Micron_4KTF25664HZ # 0b0011
-# ^ # Micron 4KTF25664HZ-1G6E1
-SPD_SOURCES += Micron_4KTF25664HZ # 0b0100
-# ^ # Micron 4KTF25664HZ-1G6E1
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101
-SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0110
-SPD_SOURCES += empty # 0b0111
-SPD_SOURCES += empty # 0b1000
-SPD_SOURCES += empty # 0b1001
-SPD_SOURCES += empty # 0b1010
-SPD_SOURCES += empty # 0b1011
-SPD_SOURCES += empty # 0b1100
-SPD_SOURCES += empty # 0b1101
-SPD_SOURCES += empty # 0b1110
-SPD_SOURCES += empty # 0b1111
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.xxd)
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
- for f in $+; \
- do xxd -rg1 $$f; \
- done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/google/auron_paine/spd/Micron_4KTF25664HZ.spd.xxd b/src/mainboard/google/auron_paine/spd/Micron_4KTF25664HZ.spd.xxd
deleted file mode 100644
index 0099da2bd9..0000000000
--- a/src/mainboard/google/auron_paine/spd/Micron_4KTF25664HZ.spd.xxd
+++ /dev/null
@@ -1,16 +0,0 @@
-0000000: 92 11 0b 03 04 19 02 02 03 11 01 08 0a 00 fe 00 ................
-0000010: 69 78 69 3c 69 11 18 81 20 08 3c 3c 01 40 83 05 ixi<i... .<<.@..
-0000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 01 02 00 ................
-0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000070: 00 00 00 00 00 80 2c 00 00 00 00 00 00 00 ad 75 ......,........u
-0000080: 34 4b 54 46 32 35 36 36 34 48 5a 2d 31 47 36 45 4KTF25664HZ-1G6E
-0000090: 31 20 45 31 80 2c 00 00 00 00 00 00 00 00 00 00 1 E1.,..........
-00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
-00000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
diff --git a/src/mainboard/google/auron_paine/spd/empty.spd.xxd b/src/mainboard/google/auron_paine/spd/empty.spd.xxd
deleted file mode 100644
index 1628923a0e..0000000000
--- a/src/mainboard/google/auron_paine/spd/empty.spd.xxd
+++ /dev/null
@@ -1,16 +0,0 @@
-0000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000020: 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-0000090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
-00000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
diff --git a/src/mainboard/google/auron_paine/spd/spd.c b/src/mainboard/google/auron_paine/spd/spd.c
deleted file mode 100644
index 7b33e66f6e..0000000000
--- a/src/mainboard/google/auron_paine/spd/spd.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbfs.h>
-#include <console/console.h>
-#include <endian.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <ec/google/chromeec/ec.h>
-#include <mainboard/google/auron_paine/ec.h>
-#include <mainboard/google/auron_paine/gpio.h>
-#include <mainboard/google/auron_paine/spd/spd.h>
-
-static void mainboard_print_spd_info(uint8_t spd[])
-{
- const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
- const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
- const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
- const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
- const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
- const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- char spd_name[SPD_PART_LEN+1] = { 0 };
-
- int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
- int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
- int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
- int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
- int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
- int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
- int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
-
- /* Module type */
- printk(BIOS_INFO, "SPD: module type is ");
- switch (spd[SPD_DRAM_TYPE]) {
- case SPD_DRAM_DDR3:
- printk(BIOS_INFO, "DDR3\n");
- break;
- case SPD_DRAM_LPDDR3:
- printk(BIOS_INFO, "LPDDR3\n");
- break;
- default:
- printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
- break;
- }
-
- /* Module Part Number */
- memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
- spd_name[SPD_PART_LEN] = 0;
- printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
-
- printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
- , banks, ranks, rows, cols);
- printk(BIOS_INFO, "density %d Mb\n", capmb);
-
- printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
- devw, busw);
-
- if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
- /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
- printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
- capmb / 8 * busw / devw * ranks);
- }
-}
-
-/* Copy SPD data for on-board memory */
-void mainboard_fill_spd_data(struct pei_data *pei_data)
-{
- int spd_bits[3] = {
- SPD_GPIO_BIT0,
- SPD_GPIO_BIT1,
- SPD_GPIO_BIT2
- };
- int spd_gpio[3];
- int spd_index;
- size_t spd_file_len;
- char *spd_file;
-
- spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
- spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
- spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
-
- spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
-
- printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
- spd_index,
- spd_bits[2], spd_gpio[2],
- spd_bits[1], spd_gpio[1],
- spd_bits[0], spd_gpio[0]);
-
- spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
- spd_index = 0;
- }
-
- if (spd_file_len < SPD_LEN)
- die("Missing SPD data.");
-
- memcpy(pei_data->spd_data[0][0],
- spd_file + (spd_index * SPD_LEN), SPD_LEN);
- /* Index 0-2 are 4GB config with both CH0 and CH1.
- * Index 4-6 are 2GB config with CH0 only. */
- if (spd_index > 3)
- pei_data->dimm_channel1_disabled = 3;
- else
- memcpy(pei_data->spd_data[1][0],
- spd_file + (spd_index * SPD_LEN), SPD_LEN);
-
- /* Make sure a valid SPD was found */
- if (pei_data->spd_data[0][0][0] == 0)
- die("Invalid SPD data.");
-
- mainboard_print_spd_info(pei_data->spd_data[0][0]);
-}
diff --git a/src/mainboard/google/auron_paine/spd/spd.h b/src/mainboard/google/auron_paine/spd/spd.h
deleted file mode 100644
index 09a48fd6e1..0000000000
--- a/src/mainboard/google/auron_paine/spd/spd.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_SPD_H
-#define MAINBOARD_SPD_H
-
-#define SPD_LEN 256
-
-#define SPD_DRAM_TYPE 2
-#define SPD_DRAM_DDR3 0x0b
-#define SPD_DRAM_LPDDR3 0xf1
-#define SPD_DENSITY_BANKS 4
-#define SPD_ADDRESSING 5
-#define SPD_ORGANIZATION 7
-#define SPD_BUS_DEV_WIDTH 8
-#define SPD_PART_OFF 128
-#define SPD_PART_LEN 18
-
-/* Auron_paine board memory configuration GPIOs */
-#define SPD_GPIO_BIT0 13
-#define SPD_GPIO_BIT1 9
-#define SPD_GPIO_BIT2 47
-
-struct pei_data;
-void mainboard_fill_spd_data(struct pei_data *pei_data);
-
-#endif
diff --git a/src/mainboard/google/auron_paine/thermal.h b/src/mainboard/google/auron_paine/thermal.h
deleted file mode 100644
index 0b66c0b58f..0000000000
--- a/src/mainboard/google/auron_paine/thermal.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef THERMAL_H
-#define THERMAL_H
-
-/* Control TDP Settings */
-#define CTL_TDP_SENSOR_ID 0 /* PECI */
-#define CTL_TDP_POWER_LIMIT 12 /* 12W */
-#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
-#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */
-#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 104
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE 95
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE 105
-
-#endif