diff options
Diffstat (limited to 'src/mainboard/google/auron_paine/spd')
7 files changed, 288 insertions, 0 deletions
diff --git a/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.xxd b/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.xxd new file mode 100644 index 0000000000..7457006ef4 --- /dev/null +++ b/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.xxd @@ -0,0 +1,16 @@ +0000000: 92 12 0b 03 04 19 02 02 03 52 01 08 0a 00 fe 00 .........R...... +0000010: 69 78 69 3c 69 11 18 81 20 08 3c 3c 01 40 83 01 ixi<i... .<<.@.. +0000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 62 00 ..............b. +0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000070: 00 00 00 00 00 80 ad 01 00 00 00 00 00 00 ff ab ................ +0000080: 48 4d 54 34 32 35 53 36 41 46 52 36 41 2d 50 42 HMT425S6AFR6A-PB +0000090: 20 20 4e 30 80 ad 00 00 00 00 00 00 00 00 00 00 N0............ +00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +00000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ diff --git a/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.xxd b/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.xxd new file mode 100644 index 0000000000..f43210615c --- /dev/null +++ b/src/mainboard/google/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.xxd @@ -0,0 +1,16 @@ +0000000: 92 13 0b 03 04 19 02 02 03 52 01 08 0a 00 fe 00 .........R...... +0000010: 69 78 69 3c 69 11 18 81 20 08 3c 3c 01 40 83 01 ixi<i... .<<.@.. +0000020: 00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 ................ +0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 62 00 ..............b. +0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000070: 00 00 00 00 00 80 ad 01 00 00 00 00 00 00 c9 c0 ................ +0000080: 48 4d 54 34 32 35 53 36 43 46 52 36 41 2d 50 42 HMT425S6CFR6A-PB +0000090: 20 20 4e 30 80 ad 00 00 00 00 00 00 00 00 00 00 N0............ +00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +00000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ diff --git a/src/mainboard/google/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron_paine/spd/Makefile.inc new file mode 100644 index 0000000000..7846c84f68 --- /dev/null +++ b/src/mainboard/google/auron_paine/spd/Makefile.inc @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 CrowdStrike Inc. <georg@crowdstrike.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +# { GPIO47, GPIO9, GPIO13 } +SPD_SOURCES = Micron_4KTF25664HZ # 0b0000 +SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001 +# ^ Hynix HMT425S6AFR6A-PBA +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0010 +# ^ Hynix HMT425S6CFR6A-PBA +SPD_SOURCES += Micron_4KTF25664HZ # 0b0011 +# ^ # Micron 4KTF25664HZ-1G6E1 +SPD_SOURCES += Micron_4KTF25664HZ # 0b0100 +# ^ # Micron 4KTF25664HZ-1G6E1 +SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101 +SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR # 0b0110 +SPD_SOURCES += empty # 0b0111 +SPD_SOURCES += empty # 0b1000 +SPD_SOURCES += empty # 0b1001 +SPD_SOURCES += empty # 0b1010 +SPD_SOURCES += empty # 0b1011 +SPD_SOURCES += empty # 0b1100 +SPD_SOURCES += empty # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.xxd) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do xxd -rg1 $$f; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab diff --git a/src/mainboard/google/auron_paine/spd/Micron_4KTF25664HZ.spd.xxd b/src/mainboard/google/auron_paine/spd/Micron_4KTF25664HZ.spd.xxd new file mode 100644 index 0000000000..0099da2bd9 --- /dev/null +++ b/src/mainboard/google/auron_paine/spd/Micron_4KTF25664HZ.spd.xxd @@ -0,0 +1,16 @@ +0000000: 92 11 0b 03 04 19 02 02 03 11 01 08 0a 00 fe 00 ................ +0000010: 69 78 69 3c 69 11 18 81 20 08 3c 3c 01 40 83 05 ixi<i... .<<.@.. +0000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 01 02 00 ................ +0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000070: 00 00 00 00 00 80 2c 00 00 00 00 00 00 00 ad 75 ......,........u +0000080: 34 4b 54 46 32 35 36 36 34 48 5a 2d 31 47 36 45 4KTF25664HZ-1G6E +0000090: 31 20 45 31 80 2c 00 00 00 00 00 00 00 00 00 00 1 E1.,.......... +00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +00000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ +00000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ diff --git a/src/mainboard/google/auron_paine/spd/empty.spd.xxd b/src/mainboard/google/auron_paine/spd/empty.spd.xxd new file mode 100644 index 0000000000..1628923a0e --- /dev/null +++ b/src/mainboard/google/auron_paine/spd/empty.spd.xxd @@ -0,0 +1,16 @@ +0000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000020: 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +0000090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +00000b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +00000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +00000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +00000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ +00000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ diff --git a/src/mainboard/google/auron_paine/spd/spd.c b/src/mainboard/google/auron_paine/spd/spd.c new file mode 100644 index 0000000000..7b33e66f6e --- /dev/null +++ b/src/mainboard/google/auron_paine/spd/spd.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <endian.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include <ec/google/chromeec/ec.h> +#include <mainboard/google/auron_paine/ec.h> +#include <mainboard/google/auron_paine/gpio.h> +#include <mainboard/google/auron_paine/spd/spd.h> + +static void mainboard_print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + break; + case SPD_DRAM_LPDDR3: + printk(BIOS_INFO, "LPDDR3\n"); + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + /* Module Part Number */ + memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " + , banks, ranks, rows, cols); + printk(BIOS_INFO, "density %d Mb\n", capmb); + + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *pei_data) +{ + int spd_bits[3] = { + SPD_GPIO_BIT0, + SPD_GPIO_BIT1, + SPD_GPIO_BIT2 + }; + int spd_gpio[3]; + int spd_index; + size_t spd_file_len; + char *spd_file; + + spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); + spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); + spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); + + spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0]; + + printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n", + spd_index, + spd_bits[2], spd_gpio[2], + spd_bits[1], spd_gpio[1], + spd_bits[0], spd_gpio[0]); + + spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + memcpy(pei_data->spd_data[0][0], + spd_file + (spd_index * SPD_LEN), SPD_LEN); + /* Index 0-2 are 4GB config with both CH0 and CH1. + * Index 4-6 are 2GB config with CH0 only. */ + if (spd_index > 3) + pei_data->dimm_channel1_disabled = 3; + else + memcpy(pei_data->spd_data[1][0], + spd_file + (spd_index * SPD_LEN), SPD_LEN); + + /* Make sure a valid SPD was found */ + if (pei_data->spd_data[0][0][0] == 0) + die("Invalid SPD data."); + + mainboard_print_spd_info(pei_data->spd_data[0][0]); +} diff --git a/src/mainboard/google/auron_paine/spd/spd.h b/src/mainboard/google/auron_paine/spd/spd.h new file mode 100644 index 0000000000..09a48fd6e1 --- /dev/null +++ b/src/mainboard/google/auron_paine/spd/spd.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +/* Auron_paine board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 13 +#define SPD_GPIO_BIT1 9 +#define SPD_GPIO_BIT2 47 + +struct pei_data; +void mainboard_fill_spd_data(struct pei_data *pei_data); + +#endif |