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-rw-r--r--src/mainboard/google/auron/variants/auron_paine/overridetree.cb4
-rw-r--r--src/mainboard/google/auron/variants/auron_yuna/overridetree.cb4
-rw-r--r--src/mainboard/google/auron/variants/buddy/overridetree.cb4
-rw-r--r--src/mainboard/google/auron/variants/gandof/overridetree.cb4
-rw-r--r--src/mainboard/google/auron/variants/lulu/overridetree.cb4
-rw-r--r--src/mainboard/google/auron/variants/samus/overridetree.cb4
6 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
index f5f3eeacdf..81110408c1 100644
--- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
@@ -8,12 +8,12 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on
-# chip soc/intel/broadwell/pch
+ chip soc/intel/broadwell/pch
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
device pci 1f.2 on end # SATA Controller
-# end
+ end
end
end
diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
index 5a64648cd1..eb33d433e8 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
@@ -8,12 +8,12 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on
-# chip soc/intel/broadwell/pch
+ chip soc/intel/broadwell/pch
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x7"
register "sata_port1_gen3_dtle" = "0x5"
device pci 1f.2 on end # SATA Controller
-# end
+ end
end
end
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index 5b6ab9f858..60fb08cbf7 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -10,7 +10,7 @@ chip soc/intel/broadwell
register "s0ix_enable" = "0"
device domain 0 on
-# chip soc/intel/broadwell/pch
+ chip soc/intel/broadwell/pch
register "sata_devslp_disable" = "0x1"
register "sio_i2c0_voltage" = "1" # 1.8V
@@ -36,6 +36,6 @@ chip soc/intel/broadwell
device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2)
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus
-# end
+ end
end
end
diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb
index 924e7d3c90..c7e2421ee8 100644
--- a/src/mainboard/google/auron/variants/gandof/overridetree.cb
+++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb
@@ -8,12 +8,12 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on
-# chip soc/intel/broadwell/pch
+ chip soc/intel/broadwell/pch
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
device pci 1f.2 on end # SATA Controller
-# end
+ end
end
end
diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb
index f5f3eeacdf..81110408c1 100644
--- a/src/mainboard/google/auron/variants/lulu/overridetree.cb
+++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb
@@ -8,12 +8,12 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on
-# chip soc/intel/broadwell/pch
+ chip soc/intel/broadwell/pch
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
device pci 1f.2 on end # SATA Controller
-# end
+ end
end
end
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index 93445756e2..d8aec0ae04 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -17,7 +17,7 @@ chip soc/intel/broadwell
register "s0ix_enable" = "0"
device domain 0 on
-# chip soc/intel/broadwell/pch
+ chip soc/intel/broadwell/pch
register "sata_port0_gen3_tx" = "0x72"
# Set I2C0 to 1.8V
@@ -37,6 +37,6 @@ chip soc/intel/broadwell
device pci 1c.2 on end # PCIe Port #3
device pci 1d.0 off end # USB2 EHCI
device pci 1f.2 on end # SATA Controller
-# end
+ end
end
end