summaryrefslogtreecommitdiff
path: root/src/mainboard/facebook/monolith/devicetree.cb
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/facebook/monolith/devicetree.cb')
-rw-r--r--src/mainboard/facebook/monolith/devicetree.cb28
1 files changed, 15 insertions, 13 deletions
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index cb3df2ee32..7c4c533326 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -181,19 +181,21 @@ chip soc/intel/skylake
# Disable Aspm
register "pcie_rp_aspm[8]" = "AspmDisabled"
- # USB 2.0 Enable all ports
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2
- register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 1
- register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 2
- register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 1
- register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M2 Port
- register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # Audio board
-
- # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 2
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 1
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 2
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 1
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 2 */
+ [1] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 1 */
+ [2] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 2 */
+ [3] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 1 */
+ [4] = USB2_PORT_SHORT(OC_SKIP), /* M2 Port */
+ [6] = USB2_PORT_SHORT(OC_SKIP), /* Audio board */
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 2 */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 1 */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 2 */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */
+ }"
register "SsicPortEnable" = "0"