diff options
Diffstat (limited to 'src/mainboard/dell')
-rw-r--r-- | src/mainboard/dell/s1850/Config.lb | 209 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/Options.lb | 228 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/auto.c | 169 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/chip.h | 5 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/cmos.layout | 80 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/debug.c | 330 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/failover.c | 46 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/irq_tables.c | 48 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/mainboard.c | 12 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/microcode_updates.c | 1563 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/mptable.c | 219 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/reset.c | 40 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/s2850_fixups.c | 23 | ||||
-rw-r--r-- | src/mainboard/dell/s1850/watchdog.c | 57 |
14 files changed, 3029 insertions, 0 deletions
diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb new file mode 100644 index 0000000000..dff583ce2c --- /dev/null +++ b/src/mainboard/dell/s1850/Config.lb @@ -0,0 +1,209 @@ +## +## Only use the option table in a normal image +## +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=131072 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/intel/E7520 # mch + device pci_domain 0 on + chip southbridge/intel/ich5r # ich5r + # USB ports + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 on end + device pci 1d.7 on end + + # -> Bridge + device pci 1e.0 on end + + # -> ISA + device pci 1f.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.6 off end + device pnp 2e.7 off end + device pnp 2e.9 off end + device pnp 2e.a on end + device pnp 2e.b off end + end + end + # -> IDE + device pci 1f.1 on end + # -> SATA + device pci 1f.2 on end + device pci 1f.3 on end + + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080" + end + device pci 00.0 on end + device pci 00.1 on end + device pci 01.0 on end + device pci 02.0 on + chip southbridge/intel/pxhd # pxhd1 + # Bus bridges and ioapics usually bus 1 + device pci 0.0 on + # On board gig e1000 + chip drivers/generic/generic + device pci 03.0 on end + device pci 03.1 on end + end + end + device pci 0.1 on end + device pci 0.2 on end + device pci 0.3 on end + end + end + device pci 04.0 on end + device pci 06.0 on end + end + device apic_cluster 0 on + chip cpu/intel/socket_mPGA604_800Mhz # cpu 0 + device apic 0 on end + end + chip cpu/intel/socket_mPGA604_800Mhz # cpu 1 + device apic 6 on end + end + end + register "intrline" = "0x00070105" +end + diff --git a/src/mainboard/dell/s1850/Options.lb b/src/mainboard/dell/s1850/Options.lb new file mode 100644 index 0000000000..8461cdb7d1 --- /dev/null +++ b/src/mainboard/dell/s1850/Options.lb @@ -0,0 +1,228 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_LOGICAL_CPUS +uses CONFIG_MAX_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses _RAMBASE +uses CONFIG_GDB_STUB +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_BTEXT +uses CC +uses HOSTCC +uses CROSS_COMPILE +uses OBJCOPY + + +### +### Build options +### + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=1048576 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Delay timer options +## Use timer2 +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=16 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=4 +default CONFIG_LOGICAL_CPUS=0 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="X6DHR" +default MAINBOARD_VENDOR= "Supermicro" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 32K heap +## +default HEAP_SIZE=0x8000 + + +### +### Compute the location and size of where this firmware image +### (linuxBIOS plus bootloader) will live in the boot rom chip. +### +default FALLBACK_SIZE=131072 + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_STREAM=1 + + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +## +## Don't enable the btext console +## +default CONFIG_CONSOLE_BTEXT=0 + + +### End Options.lb +end diff --git a/src/mainboard/dell/s1850/auto.c b/src/mainboard/dell/s1850/auto.c new file mode 100644 index 0000000000..fd70413b9a --- /dev/null +++ b/src/mainboard/dell/s1850/auto.c @@ -0,0 +1,169 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/ich5r/ich5r_early_smbus.c" +#include "northbridge/intel/E7520/raminit.h" +#include "superio/winbond/w83627hf/w83627hf.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "debug.c" +#include "watchdog.c" +#include "reset.c" +#include "s2850_fixups.c" +#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "northbridge/intel/E7520/memory_initialized.c" +#include "cpu/x86/bist.h" + + +#define SIO_GPIO_BASE 0x680 +#define SIO_XBUS_BASE 0x4880 + +#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) + +#define DEVPRES_CONFIG ( \ + DEVPRES_D0F0 | \ + DEVPRES_D1F0 | \ + DEVPRES_D2F0 | \ + DEVPRES_D3F0 | \ + DEVPRES_D4F0 | \ + DEVPRES_D6F0 | \ + 0 ) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RECVENA_CONFIG 0x0808090a +#define RECVENB_CONFIG 0x0808090a + +//void udelay(int usecs) +//{ +// int i; +// for(i = 0; i < usecs; i++) +// outb(i&0xff, 0x80); +//} + +#if 0 +static void hard_reset(void) +{ + /* enable cf9 */ + pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1); + /* reset */ + outb(0x0e, 0x0cf9); +} +#endif + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/E7520/raminit.c" +#include "sdram/generic_sdram.c" + + +static void main(unsigned long bist) +{ + /* + * + * + */ + static const struct mem_controller mch[] = { + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x00, 0), + .f1 = PCI_DEV(0, 0x00, 1), + .f2 = PCI_DEV(0, 0x00, 2), + .f3 = PCI_DEV(0, 0x00, 3), + .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, + .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + } + }; + + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + early_mtrr_init(); + if (memory_initialized()) { + asm volatile ("jmp __cpu_reset"); + } + } + /* Setup the console */ + outb(0x87,0x2e); + outb(0x87,0x2e); + pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); + w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ +// report_bist_failure(bist); + + /* MOVE ME TO A BETTER LOCATION !!! */ + /* config LPC decode for flash memory access */ + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00); + +#if 0 + display_cpuid_update_microcode(); +#endif +#if 0 + print_pci_devices(); +#endif +#if 1 + enable_smbus(); +#endif +#if 0 +// dump_spd_registers(&cpu[0]); + int i; + for(i = 0; i < 1; i++) { + dump_spd_registers(); + } +#endif + disable_watchdogs(); +// dump_ipmi_registers(); + mainboard_set_e7520_leds(); +// memreset_setup(); + sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch); +#if 0 + dump_pci_devices(); +#endif +#if 0 + dump_pci_device(PCI_DEV(0, 0x00, 0)); + dump_bar14(PCI_DEV(0, 0x00, 0)); +#endif + +#if 0 // temporarily disabled + /* Check the first 1M */ +// ram_check(0x00000000, 0x000100000); +// ram_check(0x00000000, 0x000a0000); +// ram_check(0x00100000, 0x01000000); + ram_check(0x00100000, 0x00100100); + /* check the first 1M in the 3rd Gig */ +// ram_check(0x30100000, 0x31000000); +#endif +#if 0 + ram_check(0x00000000, 0x02000000); +#endif + +#if 0 + while(1) { + hlt(); + } +#endif +} diff --git a/src/mainboard/dell/s1850/chip.h b/src/mainboard/dell/s1850/chip.h new file mode 100644 index 0000000000..b00189f049 --- /dev/null +++ b/src/mainboard/dell/s1850/chip.h @@ -0,0 +1,5 @@ +struct chip_operations mainboard_dell_s2850_ops; + +struct mainboard_dell_s2850_config { + int nothing; +}; diff --git a/src/mainboard/dell/s1850/cmos.layout b/src/mainboard/dell/s1850/cmos.layout new file mode 100644 index 0000000000..6f3cd189e3 --- /dev/null +++ b/src/mainboard/dell/s1850/cmos.layout @@ -0,0 +1,80 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/dell/s1850/debug.c b/src/mainboard/dell/s1850/debug.c new file mode 100644 index 0000000000..5546421156 --- /dev/null +++ b/src/mainboard/dell/s1850/debug.c @@ -0,0 +1,330 @@ +#define SMBUS_MEM_DEVICE_START 0x50 +#define SMBUS_MEM_DEVICE_END 0x57 +#define SMBUS_MEM_DEVICE_INC 1 + +static void print_reg(unsigned char index) +{ + unsigned char data; + + outb(index, 0x2e); + data = inb(0x2f); + print_debug("0x"); + print_debug_hex8(index); + print_debug(": 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + return; +} + +static void xbus_en(void) +{ + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); + return; +} + +static void setup_func(unsigned char func) +{ + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; +} + +static void siodump(void) +{ + int i; + unsigned char data; + + print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } +#if 0 + print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + } + + print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + setup_func(0x03); + print_reg(0xf0); + + print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + setup_func(0x02); + print_reg(0xf0); + +#endif + print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\r\n*** GPIO VALUES ***\r\n"); + data = inb(0x68a); + print_debug("\r\nGPDO 4: 0x"); + print_debug_hex8(data); + data = inb(0x68b); + print_debug("\r\nGPDI 4: 0x"); + print_debug_hex8(data); + print_debug("\r\n"); + +#if 0 + + print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + setup_func(0x0a); + print_reg(0xf0); + + print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1); + + print_debug("\r\n*** RTC REGISTERS ***\r\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff); + + print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + setup_func(0x14); + print_reg(0xf0); +#endif + return; +} + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_bar14(unsigned dev) +{ + int i; + unsigned long bar; + + print_debug("BAR 14 Dump\r\n"); + + bar = pci_read_config32(dev, 0x14); + for(i = 0; i <= 0x300; i+=4) { +#if 0 + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); +#endif + if((i%4)==0) { + print_debug("\r\n"); + print_debug_hex16(i); + print_debug_char(' '); + } + print_debug_hex32(read32(bar + i)); + print_debug_char(' '); + } + print_debug("\r\n"); +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} + +#if 0 +static void dump_spd_registers(const struct mem_controller *ctrl) +{ + int i; + print_debug("\r\n"); + for(i = 0; i < 4; i++) { + unsigned device; + device = ctrl->channel0[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + device = ctrl->channel1[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".1: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + } +} +#endif + +void dump_spd_registers(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("dimm "); + print_debug_hex8(device); + + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + status = smbus_read_byte(device, i); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} + +void dump_ipmi_registers(void) +{ + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("ipmi "); + print_debug_hex8(device); + + for(i = 0; (i < 8) ; i++) { + unsigned char byte; + status = smbus_read_byte(device, 2); + if (status < 0) { + print_debug("bad device: "); + print_debug_hex8(-status); + print_debug("\r\n"); + break; + } + print_debug_hex8(status); + print_debug_char(' '); + } + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} diff --git a/src/mainboard/dell/s1850/failover.c b/src/mainboard/dell/s1850/failover.c new file mode 100644 index 0000000000..5029d98611 --- /dev/null +++ b/src/mainboard/dell/s1850/failover.c @@ -0,0 +1,46 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "pc80/mc146818rtc_early.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/intel/E7520/memory_initialized.c" + +static unsigned long main(unsigned long bist) +{ + /* Did just the cpu reset? */ + if (memory_initialized()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto cpu_reset; + } + } + + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} diff --git a/src/mainboard/dell/s1850/irq_tables.c b/src/mainboard/dell/s1850/irq_tables.c new file mode 100644 index 0000000000..d0e7be1cd9 --- /dev/null +++ b/src/mainboard/dell/s1850/irq_tables.c @@ -0,0 +1,48 @@ +/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
+ *
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*17, /* there can be total 17 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x24d0, /* Device */
+ 0, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xc4, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x02<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x04<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x05<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x00,(0x06<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x05,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
+ {0x01,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
+ {0x00,(0x1d<<3)|0x0, {{0x60, 0xccf8}, {0x63, 0xccf8}, {0x62, 0xccf8}, {0x6b, 0x0ccf8}}, 0x0, 0x0},
+ {0x09,(0x05<<3)|0x0, {{0x68, 0xccf8}, {0x69, 0xccf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x09,(0x06<<3)|0x0, {{0x6b, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x09,(0x0d<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x09,(0x03<<3)|0x0, {{0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0xccf8}, {0x63, 0x0ccf8}}, 0x0, 0x0},
+ {0x06,(0x07<<3)|0x0, {{0x60, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x07,(0x08<<3)|0x0, {{0x61, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x02,(0x05<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x04,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x1, 0x0},
+ {0x08,(0x00<<3)|0x0, {{0x60, 0xccf8}, {0x61, 0xccf8}, {0x62, 0xccf8}, {0x63, 0x0ccf8}}, 0x2, 0x0},
+ {0x02,(0x0e<<3)|0x0, {{0x62, 0xccf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
+
diff --git a/src/mainboard/dell/s1850/mainboard.c b/src/mainboard/dell/s1850/mainboard.c new file mode 100644 index 0000000000..d1b419df6c --- /dev/null +++ b/src/mainboard/dell/s1850/mainboard.c @@ -0,0 +1,12 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include "chip.h" + +struct chip_operations mainboard_dell_s2850_ops = { + CHIP_NAME("Dell S2850") +}; + diff --git a/src/mainboard/dell/s1850/microcode_updates.c b/src/mainboard/dell/s1850/microcode_updates.c new file mode 100644 index 0000000000..b2e72ab616 --- /dev/null +++ b/src/mainboard/dell/s1850/microcode_updates.c @@ -0,0 +1,1563 @@ +/* WARNING - Intel has a new data structure that has variable length
+ * microcode update lengths. They are encoded in int 8 and 9. A
+ * dummy header of nulls must terminate the list.
+ */
+
+static const unsigned int microcode_updates[] __attribute__ ((aligned(16))) = {
+ /*
+ Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
+ These microcode updates are distributed for the sole purpose of
+ installation in the BIOS or Operating System of computer systems
+ which include an Intel P6 family microprocessor sold or distributed
+ to or by you. You are authorized to copy and install this material
+ on such systems. You are not authorized to use this material for
+ any other purpose.
+ */
+
+ /* M1DF3413.TXT - Noconoa D-0 */
+
+ 0x00000001, /* Header Version */
+ 0x00000013, /* Patch ID */
+ 0x07302004, /* DATE */
+ 0x00000f34, /* CPUID */
+ 0x95f183f0, /* Checksum */
+ 0x00000001, /* Loader Version */
+ 0x0000001d, /* Platform ID */
+ 0x000017d0, /* Data size */
+ 0x00001800, /* Total size */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+
+ 0x9fbf327a,
+ 0x2b41b451,
+ 0xb2abaca8,
+ 0x6b62b8e0,
+ 0x0af32c41,
+ 0x12ca6048,
+ 0x5bd55ae6,
+ 0xb90dfc1d,
+ 0x565fe2b2,
+ 0x326b1718,
+ 0x61f3a40d,
+ 0xceb53db3,
+ 0x14fb5261,
+ 0xbb23b6c3,
+ 0x9d7c0466,
+ 0xde90a25e,
+ 0x9450e9bb,
+ 0x497bd6e4,
+ 0x97d1041a,
+ 0x1831013f,
+ 0x6e6fa37e,
+ 0x0b5c1d03,
+ 0x5eae4db2,
+ 0xc029d9e3,
+ 0x5373bca3,
+ 0xe15fccca,
+ 0x39043db0,
+ 0xaeb0ea0c,
+ 0x62b4e391,
+ 0x0b280c6b,
+ 0x279eb9d3,
+ 0x98d95ada,
+ 0xc1cb45a7,
+ 0x06917bda,
+ 0xdde8aafa,
+ 0xdff9d15c,
+ 0xd07f8f0a,
+ 0x192bcf9d,
+ 0xf77de31f,
+ 0xadf8be55,
+ 0x3f7a5d95,
+ 0x0e2140b6,
+ 0xf0c75eec,
+ 0x3254876a,
+ 0x684a1698,
+ 0x4ad0cca7,
+ 0x6d705304,
+ 0xf957d91b,
+ 0xe8bb864a,
+ 0x440d636c,
+ 0xaf4d7d06,
+ 0x12680ecf,
+ 0x5d0f9e53,
+ 0x60148a5d,
+ 0x81008364,
+ 0x243a8aed,
+ 0xd55976de,
+ 0xd6a84520,
+ 0x932d4b77,
+ 0xe67e5f19,
+ 0x7dba0e47,
+ 0xfee3b153,
+ 0x46b6a20c,
+ 0x2594e6f6,
+ 0x210cab0f,
+ 0xf6e47d5d,
+ 0xe38276e4,
+ 0x90fc2728,
+ 0x9faefa11,
+ 0xc972217c,
+ 0xc8d079dd,
+ 0x5f7dc338,
+ 0x106f7b7b,
+ 0xd04c0a1c,
+ 0x0eca300e,
+ 0x1ddae8a6,
+ 0x6e7fd42e,
+ 0xa56c514d,
+ 0x56a4e255,
+ 0x975ea2bf,
+ 0x0eaa78cc,
+ 0x0c3e284f,
+ 0xbacb6c71,
+ 0x1645006f,
+ 0xe9a2b955,
+ 0x0677c019,
+ 0x24b33da0,
+ 0x62f200fa,
+ 0x234238c4,
+ 0x81d5ad79,
+ 0x9f754bc9,
+ 0xeffd5016,
+ 0x041b2cc2,
+ 0x2f020bc7,
+ 0x4fcd68b8,
+ 0x22c3579c,
+ 0x4804a114,
+ 0xc42db3ea,
+ 0x7cde8141,
+ 0x47e167c8,
+ 0x01aa38cc,
+ 0x74a5c25e,
+ 0xe0c48d67,
+ 0x562365ad,
+ 0x38321e57,
+ 0x0395885a,
+ 0x6888323e,
+ 0xd6fc518f,
+ 0x1854b64c,
+ 0x06a58476,
+ 0x3662f898,
+ 0xe2bcdaee,
+ 0x84c40693,
+ 0xef09d374,
+ 0x353cc799,
+ 0x742223d4,
+ 0x05b3c99b,
+ 0x0c51ee45,
+ 0xd145824a,
+ 0xac30806c,
+ 0x2ed70c0d,
+ 0x71ae10ff,
+ 0xbf491854,
+ 0x3e1f03b4,
+ 0x76bfd6cd,
+ 0x1449aa8a,
+ 0xf954d3fb,
+ 0xf8c7c940,
+ 0x70233f85,
+ 0x0729e257,
+ 0x10bb8936,
+ 0xc35bb5b5,
+ 0x95d78b5c,
+ 0xcc1ba443,
+ 0x6f507126,
+ 0xa607cfd0,
+ 0xce22f2f3,
+ 0x5134ed8c,
+ 0xec8d2f06,
+ 0xa92413d5,
+ 0xb973f431,
+ 0x16e136dd,
+ 0xf7d41bed,
+ 0x01b002fe,
+ 0x646ed771,
+ 0x76ea3d26,
+ 0x5024af20,
+ 0x84270f51,
+ 0x9b3d7820,
+ 0x2454a2c6,
+ 0xc1f072ed,
+ 0x155e864f,
+ 0x4c39a6e5,
+ 0x928206e5,
+ 0x9d1685f5,
+ 0x45542ee7,
+ 0x1fd27d9e,
+ 0x5f2dd9ff,
+ 0x222005eb,
+ 0x354e8a55,
+ 0x1f0de29a,
+ 0xb86dc696,
+ 0x9eafafad,
+ 0x191b197e,
+ 0x0e0900e1,
+ 0xe0ac42bb,
+ 0x3143236f,
+ 0x44177def,
+ 0x05259274,
+ 0xb21af44a,
+ 0x6ddee4df,
+ 0xc7b56255,
+ 0xb6b1d39d,
+ 0x218f9070,
+ 0x96545a42,
+ 0x98cc2d4a,
+ 0xb21bac9e,
+ 0x83e12d44,
+ 0x2ef4fb39,
+ 0xbc03528f,
+ 0x9485af58,
+ 0xd9f1e6ab,
+ 0xde7607e6,
+ 0x3b398733,
+ 0x9cd9b1a9,
+ 0xabd77984,
+ 0xcce18826,
+ 0x701c5c21,
+ 0xe6591cbf,
+ 0x07a9b9e1,
+ 0x69459c90,
+ 0xe0cdcad6,
+ 0xc4c6c4b6,
+ 0x12748024,
+ 0x4a33c567,
+ 0x7d26a37e,
+ 0xcae163bf,
+ 0xeb7547fa,
+ 0xccc6a01c,
+ 0x3cb8abb8,
+ 0x64aa67b2,
+ 0x51ddf6de,
+ 0xbfe1b905,
+ 0x50923949,
+ 0xacfa43af,
+ 0x1fdb5a44,
+ 0x091533cb,
+ 0x7c92e5dc,
+ 0x1c5d0d3e,
+ 0x195271f5,
+ 0x96e73a4a,
+ 0xe1b11968,
+ 0xb42906f2,
+ 0x5a2940b3,
+ 0x611283e9,
+ 0x65829161,
+ 0x5d1357b7,
+ 0x019428ad,
+ 0x836c5c3c,
+ 0xc0e5e169,
+ 0xd360e424,
+ 0x257a9d69,
+ 0xdca09040,
+ 0x85f1c060,
+ 0xae7cae79,
+ 0xa5ddcfd6,
+ 0xdba8f68e,
+ 0xd98df596,
+ 0xe6e3cd51,
+ 0xcfb2be8f,
+ 0x368fe6cd,
+ 0x58486b75,
+ 0x791f1a48,
+ 0xf81a61f2,
+ 0x58a38155,
+ 0x30a86547,
+ 0xd7fb2db1,
+ 0x300e0b1d,
+ 0x3f838461,
+ 0xf278805a,
+ 0x49529931,
+ 0x601d5649,
+ 0xe500ba1a,
+ 0xc4f78965,
+ 0xe10ed02d,
+ 0x1f777ebd,
+ 0x2db1d17d,
+ 0x48a22e6a,
+ 0x5a14b738,
+ 0xdcf899e0,
+ 0xc845bd04,
+ 0xd04a52b9,
+ 0xf2f19b06,
+ 0xdb5ba97a,
+ 0xf05605ff,
+ 0xc787b72c,
+ 0x9f197770,
+ 0x87b31150,
+ 0x3ff00d57,
+ 0x89d1dcb3,
+ 0x07528ff4,
+ 0x4105fcef,
+ 0xb087de2e,
+ 0x3bd333a5,
+ 0x84a094f4,
+ 0x9ab8fb97,
+ 0xc9bba063,
+ 0x664c52e5,
+ 0x27fd05e4,
+ 0x3f0e491d,
+ 0xab8f4b9a,
+ 0x344a0249,
+ 0x727dd74f,
+ 0x29587211,
+ 0xbba262b9,
+ 0x319ecbb3,
+ 0xec54b023,
+ 0xd0fa096d,
+ 0x3d223f23,
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+ 0x8356c7ae,
+ 0x32ecb208,
+ 0x900c89ed,
+ 0x2a206ff5,
+ 0x7eed5032,
+ 0x5b55b25d,
+ 0xf98d6df2,
+ 0xf52bc8a9,
+ 0x1aa2f5fe,
+ 0x1d33c0bf,
+ 0x3cd34e89,
+ 0x9a0da4ae,
+ 0x1c205917,
+ 0x7ca784cd,
+ 0xf7dda662,
+ 0xad97f3ff,
+ 0x525c53ec,
+ 0x024f11ff,
+ 0x32c3ae5b,
+ 0xbf372800,
+ 0x8ff15f4d,
+ 0x7605d019,
+ 0x0dae7740,
+ 0x5f5dd0ef,
+ 0x0f6c37d0,
+ 0xee6fa91e,
+ 0xb9f51051,
+ 0x39a9f0d1,
+ 0x22bf03fb,
+ 0x485a0922,
+ 0x7384b30e,
+ 0x85ba7f16,
+ 0xb1f0a524,
+ 0x7e9c5113,
+ 0x240d9306,
+ 0x1ca7b0ea,
+ 0x18a0d114,
+ 0x76b64213,
+ 0x31212cc0,
+ 0xc9dca5c3,
+ 0x69f2ae52,
+ 0x545caa7c,
+ 0xfb2ff045,
+ 0x3f3a1af5,
+ 0xe75b6913,
+ 0x775a1c79,
+ 0x4627e25f,
+ 0x90a14b97,
+ 0x06456383,
+ 0x3d52cf69,
+ 0xfb2492c3,
+ 0x39f25a22,
+ 0x81f68c55,
+ 0x87b14e15,
+ 0x0920af5d,
+ 0xe2585678,
+ 0x0671e46d,
+ 0xb77ddb67,
+ 0x3948c4b3,
+ 0x122dddef,
+ 0xd0726172,
+ 0xd3302234,
+ 0x58bab4e4,
+ 0x195ac247,
+ 0x082459f0,
+ 0x18a2566d,
+ 0xbf56078d,
+ 0x116ed409,
+ 0x5ccc0f80,
+ 0xbae0b4ca,
+ 0x21a6325d,
+ 0x7e1f0c40,
+ 0x595326d4,
+ 0x518b2244,
+ 0x8ab3cdb7,
+ 0xbe6b4835,
+ 0xfc39f8ac,
+ 0x63b167aa,
+ 0x194f070d,
+ 0xed3d0416,
+ 0xae16758a,
+ 0xb9bb6bbf,
+ 0x477d9c85,
+ 0x9808c304,
+ 0xe1d8cec4,
+ 0x7ee22e17,
+ 0x0a7a9d7f,
+ 0xcc98173a,
+ 0x5f78dc21,
+ 0x364bc95e,
+ 0xb54608d9,
+ 0x5d4d70ea,
+ 0x083a7f79,
+ 0x59ffbd73,
+ 0x4f3e9eaf,
+ 0x68755ad4,
+ 0xab254689,
+ 0x11bf09a8,
+ 0xbbc40098,
+ 0x969ca3eb,
+ 0x30eee9d2,
+ 0xe35bc37e,
+ 0xcb2d678f,
+ 0x7846876b,
+ 0xf0d28ae7,
+ 0xc092fbb2,
+ 0x321b344a,
+ 0xcc5ee81b,
+ 0xd2afa00f,
+ 0xfeccd86a,
+ 0x6e5e55c2,
+ 0x2b5543ea,
+ 0x810e4009,
+ 0xea2d8e20,
+ 0x6acae3b9,
+ 0x3828e15e,
+ 0xe1e4821c,
+ 0xf429da70,
+ 0x35f6565c,
+ 0x64b1baa8,
+ 0x350e9583,
+ 0xd2522d4f,
+ 0x5e28a3f1,
+ 0x949ff0aa,
+ 0x3c1b5694,
+ 0x146dde1f,
+ 0x6f3430e1,
+ 0x71c077b7,
+ 0x4d145924,
+ 0xe431cd28,
+ 0xb315cfde,
+ 0xa0365a4a,
+ 0x473de1aa,
+ 0xcbe4e999,
+ 0x319906e9,
+ 0xad0fea9c,
+ 0x89e4e72d,
+ 0x9dbba94d,
+ 0xd395c1c5,
+ 0xa1fff11a,
+ 0x8447e120,
+ 0xe5c59100,
+ 0xa07cb778,
+ 0x8f30a039,
+ 0xed78facb,
+ 0x86de9373,
+ 0x550c4889,
+ 0xce71e3a8,
+ 0x06167b3a,
+ 0x5abdd9a3,
+ 0xc8a9e48d,
+ 0xe3312905,
+ 0x7a63a146,
+ 0xc0f19763,
+ 0xda0cf9db,
+ 0x1d708306,
+ 0x0e41f0ba,
+ 0x4c7939fe,
+ 0x768e48c2,
+ 0xe925fd31,
+ 0x309e7870,
+ 0xfc261b87,
+ 0xc897b2de,
+ 0x6c714792,
+ 0x41c7fbac,
+ 0x57d0b3c3,
+ 0x4fa82a55,
+ 0xd56b4a87,
+ 0x81e5cabc,
+ 0xb260cb7b,
+ 0x520927ab,
+ 0x20d0ab46,
+ 0xc9f92ddf,
+ 0x81f4a21d,
+ 0xfc5a0ca2,
+ 0x95d16aad,
+ 0xe54d7847,
+ 0x6080cc07,
+ 0x0df73f7e,
+ 0xaa8d5187,
+ 0x97a0bc12,
+ 0xb22c5e68,
+ 0x0954d7dc,
+ 0x3368ab5a,
+ 0xd12541df,
+ 0x58119260,
+ 0xe5b0e1df,
+ 0x25027fa4,
+ 0x5780425d,
+ 0x29bb8791,
+ 0x4100b7a9,
+ 0x076b3519,
+ 0x15e0ebb4,
+ 0xe5fb9273,
+ 0x6dbf07e7,
+ 0x1f82bddd,
+ 0x03691b6b,
+ 0xbacef28c,
+ 0x9909ed5a,
+ 0x98886793,
+ 0x544f9a82,
+ 0x9d9749d0,
+ 0x38441606,
+ 0xc4a9f4d2,
+ 0x6ce2bcf1,
+ 0x1c7c3abd,
+ 0x62c621f1,
+ 0x871ee1e4,
+ 0xa83930ce,
+ 0xbe1ee459,
+ 0xd61f1ca4,
+ 0x8c4450e5,
+ 0x98031ca9,
+ 0xe52f54e2,
+ 0xd0c4c737,
+ 0x76074160,
+ 0xbf050c3b,
+ 0x2603af14,
+ 0x43cbb0bc,
+ 0xc631b9e8,
+ 0x26030719,
+ 0x993f570c,
+ 0xdda34038,
+ 0xe34a9793,
+ 0x337a124c,
+ 0x2aa8af16,
+ 0xf80d7473,
+ 0xf01d9397,
+ 0x68e1afb9,
+ 0x0eb37ad2,
+ 0xf71969f9,
+ 0xdf020552,
+ 0x75aa9b30,
+ 0xffa210cf,
+ 0x543c414f,
+ 0xa1e3faec,
+ 0x40891d7e,
+ 0x6b48a6c5,
+ 0xec09a1a0,
+ 0x97a31f2a,
+ 0x5a6be2d7,
+ 0xd06e492b,
+ 0xc54290af,
+ 0xcb524021,
+ 0x420e8c4d,
+ 0xfb135c17,
+ 0x2bfc8adb,
+ 0x9f0cfb46,
+ 0x564db712,
+ 0x7a97a227,
+ 0x8bb98daf,
+ 0xdd0d6180,
+ 0x3d28b9e3,
+ 0xe505050f,
+ 0x19a9868e,
+ 0x7bf5685f,
+ 0x35d698c4,
+ 0xce7e1de3,
+ 0x360a64af,
+ 0x25a1f022,
+ 0xe26c1d04,
+ 0x5b3fb364,
+ 0x932f25f7,
+ 0x9a2aa00d,
+ 0xc50fb773,
+ 0xec45ea3a,
+ 0x22ddf8e4,
+ 0xafb6a6c8,
+ 0x876d04f7,
+ 0xd9c86c3c,
+ 0xd54bee2d,
+ 0xf4e28199,
+ 0xc3456776,
+ 0x04c3107b,
+ 0xbf914e9d,
+ 0x23fefaa5,
+ 0x0931a133,
+ 0x41467758,
+ 0x8ec49707,
+ 0x5ed48709,
+ 0xd11c2de8,
+ 0xb687a0b9,
+ 0xdc908383,
+ 0xd8037ff3,
+ 0xd4311a9f,
+ 0xd00aeb6a,
+ 0xfe54df3b,
+ 0x9c51ce4d,
+ 0x36956408,
+ 0xcd28ef09,
+ 0xc68932b0,
+ 0x7c31e782,
+ 0x28b4723c,
+ 0xededacc2,
+ 0x6ddbac6b,
+ 0x775a7fc1,
+ 0x6909906f,
+ 0xa774123c,
+ 0xf63145ad,
+ 0x287b191e,
+ 0x59d79300,
+ 0xbf76a2fc,
+ 0xfbaf9207,
+ 0x2fe5b7f6,
+ 0xebe7c103,
+ 0x71ac0a8d,
+ 0x2028c3c7,
+ 0xd2cb4917,
+ 0xd74a4ee4,
+ 0xfce405d8,
+ 0xad83fd0f,
+ 0x8f9ec3da,
+ 0xaab2301c,
+ 0xc6f1339f,
+ 0xc652bced,
+ 0xe378b272,
+ 0x18e1ff34,
+ 0x9ec778b6,
+ 0xce1a3883,
+ 0x7c5e5eaf,
+ 0xd16ec37a,
+ 0xa69e45f4,
+ 0xc36cd4aa,
+ 0x045b391f,
+ 0x5a2a08f1,
+ 0x4dd8d53e,
+ 0xd64796ec,
+ 0x4476fc28,
+ 0x18dbaa50,
+ 0x00fb2407,
+ 0x177db915,
+ 0x5969758b,
+ 0x3030964a,
+ 0x81d6485b,
+ 0x7d2e12b0,
+ 0x624d6c5f,
+ 0x0746bbc0,
+ 0xe669d150,
+ 0x0465eef7,
+ 0x09764011,
+ 0x551995e4,
+ 0x8422dedf,
+ 0x0ca56194,
+ 0x293eab2e,
+ 0xf20a137a,
+ 0x55117fc2,
+ 0xbc5431af,
+ 0x064751fa,
+ 0xc0dafdb2,
+ 0x6c3b1d4f,
+ 0xeac335b3,
+ 0x71173afc,
+ 0x31c84b7c,
+ 0xfef2b4ab,
+ 0x59ca5fa2,
+ 0x664c8b4e,
+ 0x7dfd560b,
+ 0xdb0daff3,
+ 0x51f87bfa,
+ 0x58015d2e,
+ 0x67a827b4,
+ 0x62cebc1a,
+ 0x24b37298,
+ 0x75b589be,
+ 0x874f1800,
+ 0x277b795c,
+ 0xf762489e,
+ 0x87d00752,
+ 0x9be45ed1,
+ 0x296ec120,
+ 0x61162480,
+ 0x792e8a2c,
+ 0x3b631590,
+ 0xe33ba0cf,
+ 0x542ac23c,
+ 0xe1e8cffa,
+ 0xfc084cd8,
+ 0xc115ad31,
+ 0x71559928,
+ 0x791f1e33,
+ 0x662ed92b,
+ 0x7222c76d,
+ 0x02dcd566,
+ 0x8db9b4d4,
+ 0xa5f344c8,
+ 0x15806b12,
+ 0x81e572f7,
+ 0x3b3fbe25,
+ 0x2133b413,
+ 0x2d68a367,
+ 0x356f6ce7,
+ 0xcd6dfed1,
+ 0xd8b3a26e,
+ 0xe9d328da,
+ 0x127425ab,
+ 0x83a60aac,
+ 0x8cc26190,
+ 0x7f87ab26,
+ 0x56faab5f,
+ 0x76d0feaa,
+ 0x4b25dd10,
+ 0x4f6286ea,
+ 0x79298d06,
+ 0x8002bf83,
+ 0x2977c85e,
+ 0xd3b3d19a,
+ 0xa92bf132,
+ 0xa280efd8,
+ 0x83f7ad6e,
+ 0x748969c7,
+ 0x25ff411d,
+ 0x3854d3a8,
+ 0x55746aa2,
+ 0x00db5c54,
+ 0x36949e0d,
+ 0x40402ab6,
+ 0x1a720211,
+ 0xe02ce823,
+ 0x4ac104a2,
+ 0x214d2e4b,
+ 0x267e5c83,
+ 0x38a3a483,
+ 0xd1da1f67,
+ 0x0c68db2c,
+ 0xd7035d63,
+ 0xa29393bb,
+ 0xa5743519,
+ 0xcb97c84e,
+ 0xa853974f,
+ 0x147360a0,
+ 0x2df9b3f4,
+ 0x0aff129e,
+ 0x177d687f,
+ 0x87eff911,
+ 0x6c60b354,
+ 0x6c356c38,
+ 0x7d480965,
+ 0xbb06a193,
+ 0x25b0568e,
+ 0x6fd6da9a,
+ 0x82b64f14,
+ 0x3d267a78,
+ 0xf100b6a7,
+ 0x32c74539,
+ 0x6042e152,
+ 0x4548276e,
+ 0xa3a32b70,
+ 0xf029fe15,
+ 0xa9b8bd2f,
+ 0x5618eee4,
+ 0x9815a5f0,
+ 0x89fb2850,
+ 0xa9261b26,
+ 0xded9e505,
+ 0x37e9d749,
+ 0xdc4aeb78,
+ 0x9e634f7a,
+ 0xcf638d2d,
+ 0x6b679f92,
+ 0x2b64911d,
+ 0xe6d1312f,
+ 0x88b3e76a,
+ 0x56311f62,
+ 0x00916de7,
+ 0x39d0bc61,
+ 0x8ac09356,
+ 0x47abcfce,
+ 0x324cb73e,
+ 0xfadcd0a8,
+ 0x2f2fbca8,
+ 0x945eda22,
+ 0xba23cab1,
+ 0xf9fb4212,
+ 0x1fa71d45,
+ 0x867a034e,
+ 0x3bee5db1,
+ 0xf54adced,
+ 0x6633ba77,
+ 0xe1eb4f1e,
+ 0x97ef01f6,
+ 0x57fd3b32,
+ 0x5234d80d,
+ 0xe8ee95f3,
+ 0x5dc990bf,
+ 0xaba833e1,
+/* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+
diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c new file mode 100644 index 0000000000..f0624751b3 --- /dev/null +++ b/src/mainboard/dell/s1850/mptable.c @@ -0,0 +1,219 @@ +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "DELL "; + static const char productid[12] = "S2850 "; + struct mp_config_table *mc; + unsigned char bus_num; + unsigned char bus_isa; + unsigned char bus_pxhd_1; + unsigned char bus_pxhd_2; + unsigned char bus_pxhd_3; + unsigned char bus_pxhd_4; + unsigned char bus_ich5r_1; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + { + device_t dev; + + /* ich5r */ + dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); + if (dev) { + bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + else { + printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n"); + + bus_ich5r_1 = 7; + bus_isa = 8; + } + /* pxhd-1 */ + dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); + if (dev) { + bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:00.0, using defaults\n"); + + bus_pxhd_1 = 2; + } + /* pxhd-2 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); + if (dev) { + bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 1:00.2, using defaults\n"); + + bus_pxhd_2 = 3; + } + + /* pxhd-3 */ + dev = dev_find_slot(0, PCI_DEVFN(0x4,0)); + if (dev) { + bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 0:04.0, using defaults\n"); + + bus_pxhd_3 = 5; + } + /* pxhd-4 */ + dev = dev_find_slot(0, PCI_DEVFN(0x06,0)); + if (dev) { + bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk_debug("ERROR - could not find PCI 0:06.0, using defaults\n"); + + bus_pxhd_4 = 6; + } + + } + + /* define bus and isa numbers */ + for(bus_num = 0; bus_num < bus_isa; bus_num++) { + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, bus_isa, "ISA "); + + /* IOAPIC handling */ + + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + { + struct resource *res; + device_t dev; + /* pxhd apic 3 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x03, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n"); + } + /* pxhd apic 4 */ + dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x04, 0x20, res->base); + } + } + else { + printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n"); + } + } + /* ISA backward compatibility interrupts */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x01, 0x02, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, 0x02, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x03, 0x02, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x04, 0x02, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x74, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x06, 0x02, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x76, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x08, 0x02, 0x08); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x09, 0x02, 0x09); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x77, 0x02, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x75, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0c, 0x02, 0x0c); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0d, 0x02, 0x0d); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0e, 0x02, 0x0e); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0f, 0x02, 0x0f); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x74, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7c, 0x02, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, 0x7d, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_1, 0x08, 0x03, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_1, 0x0c, 0x03, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_1, 0x0d, 0x03, 0x07); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_2, 0x08, 0x04, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_ich5r_1, 0x04, 0x02, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_pxhd_4, 0x00, 0x02, 0x10); +#if 0 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + (bus_isa - 1), 0x04, 0x02, 0x10); +#endif + /* Standard local interrupt assignments */ +#if 0 + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, MP_APIC_ALL, 0x00); +#endif + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + bus_isa, 0x00, MP_APIC_ALL, 0x01); + + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} + diff --git a/src/mainboard/dell/s1850/reset.c b/src/mainboard/dell/s1850/reset.c new file mode 100644 index 0000000000..874bfc4848 --- /dev/null +++ b/src/mainboard/dell/s1850/reset.c @@ -0,0 +1,40 @@ +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#ifndef __ROMCC__ +#include <device/device.h> +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) +#define PCI_DEV_INVALID 0 + +static inline device_t pci_locate_device(unsigned pci_id, device_t from) +{ + return dev_find_device(pci_id >> 16, pci_id & 0xffff, from); +} +#endif + +void soft_reset(void) +{ + outb(0x04, 0xcf9); +} +void hard_reset(void) +{ + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); +} +void full_reset(void) +{ + device_t dev; + /* Enable power on after power fail... */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0); + if (dev != PCI_DEV_INVALID) { + unsigned byte; + byte = pci_read_config8(dev, 0xa4); + byte &= 0xfe; + pci_write_config8(dev, 0xa4, byte); + + } + outb(0x0e, 0xcf9); +} + + diff --git a/src/mainboard/dell/s1850/s2850_fixups.c b/src/mainboard/dell/s1850/s2850_fixups.c new file mode 100644 index 0000000000..82c070b0c1 --- /dev/null +++ b/src/mainboard/dell/s1850/s2850_fixups.c @@ -0,0 +1,23 @@ +#include <arch/romcc_io.h> + +static void mch_reset(void) +{ + return; +} + + + +static void mainboard_set_e7520_pll(unsigned bits) +{ + return; +} + + +static void mainboard_set_e7520_leds(void) +{ + return; +} + + + + diff --git a/src/mainboard/dell/s1850/watchdog.c b/src/mainboard/dell/s1850/watchdog.c new file mode 100644 index 0000000000..e22ffeef80 --- /dev/null +++ b/src/mainboard/dell/s1850/watchdog.c @@ -0,0 +1,57 @@ +#include <device/pnp_def.h> + +#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) +#define NSC_WDBASE 0x600 +#define ICH5_WDBASE 0x400 +#define ICH5_GPIOBASE 0x500 + +static void disable_sio_watchdog(device_t dev) +{ +#if 0 + /* FIXME move me somewhere more appropriate */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); + /* disable the sio watchdog */ + outb(0, NSC_WDBASE + 0); + pnp_set_enable(dev, 0); +#endif +} + +static void disable_ich5_watchdog(void) +{ + /* FIXME move me somewhere more appropriate */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) { + die("Missing ich5?"); + } + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Set and enable acpibase */ + pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); + pci_write_config8(dev, 0x44, 0x10); + base = ICH5_WDBASE + 0x60; + + /* Set bit 11 in TCO1_CNT */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); +} + + +static void disable_watchdogs(void) +{ +// disable_sio_watchdog(NSC_WD_DEV); + disable_ich5_watchdog(); + print_debug("Watchdogs disabled\r\n"); +} + |