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-rw-r--r--src/mainboard/dell/optiplex_9020/Makefile.mk3
-rw-r--r--src/mainboard/dell/optiplex_9020/bootblock.c31
-rw-r--r--src/mainboard/dell/optiplex_9020/cmos.default1
-rw-r--r--src/mainboard/dell/optiplex_9020/cmos.layout3
-rw-r--r--src/mainboard/dell/optiplex_9020/mainboard.c387
-rw-r--r--src/mainboard/dell/optiplex_9020/sch5555_ec.c54
-rw-r--r--src/mainboard/dell/optiplex_9020/sch5555_ec.h10
7 files changed, 465 insertions, 24 deletions
diff --git a/src/mainboard/dell/optiplex_9020/Makefile.mk b/src/mainboard/dell/optiplex_9020/Makefile.mk
index 6ca2f2afaa..08e2e53577 100644
--- a/src/mainboard/dell/optiplex_9020/Makefile.mk
+++ b/src/mainboard/dell/optiplex_9020/Makefile.mk
@@ -2,4 +2,5 @@
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-bootblock-y += bootblock.c
+ramstage-y += sch5555_ec.c
+bootblock-y += bootblock.c sch5555_ec.c
diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
index 2837cf9cf1..00559105a7 100644
--- a/src/mainboard/dell/optiplex_9020/bootblock.c
+++ b/src/mainboard/dell/optiplex_9020/bootblock.c
@@ -4,29 +4,14 @@
#include <device/pnp_ops.h>
#include <superio/smsc/sch555x/sch555x.h>
#include <southbridge/intel/lynxpoint/pch.h>
-
-static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
-{
- // Clear EC-to-Host mailbox
- uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
- outb(tmp, SCH555x_EMI_IOBASE + 1);
-
- // Send address and value to the EC
- sch555x_emi_write16(0, (addr1 * 2) | 0x101);
- sch555x_emi_write32(4, val | (addr2 << 16));
-
- // Wait for acknowledgement message from EC
- outb(1, SCH555x_EMI_IOBASE);
- size_t timeout = 0;
- do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
-}
+#include "sch5555_ec.h"
struct ec_init_entry {
uint16_t addr;
uint8_t val;
};
-static void ec_init(void)
+static void bootblock_ec_init(void)
{
/*
* Tables from CORE_PEI
@@ -42,7 +27,7 @@ static void ec_init(void)
};
for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i)
- ec_write(2, init_table1[i].addr, init_table1[i].val);
+ sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val);
static const struct ec_init_entry init_table2[] = {
{0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f},
@@ -60,7 +45,7 @@ static void ec_init(void)
};
for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i)
- ec_write(1, init_table2[i].addr, init_table2[i].val);
+ sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val);
/*
* Table from PeiHwmInit
@@ -89,7 +74,7 @@ static void ec_init(void)
};
for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i)
- ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val);
+ sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val);
}
#define SCH555x_IOBASE 0x2e
@@ -108,9 +93,9 @@ void mainboard_config_superio(void)
outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
- // Magic EC init
- ec_init();
+ // Perform bootblock EC initialization
+ bootblock_ec_init();
- // Magic EC init is needed for UART1 initialization to work
+ // Bootblock EC initialization is required for UART1 to work
sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
index cd4046f1ab..6c4a2a1be7 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
@@ -3,3 +3,4 @@ boot_option=Fallback
debug_level=Debug
nmi=Disable
power_on_after_fail=Disable
+fan_full_speed=Disable
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
index c9ba76c78f..d10ad95b23 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
@@ -21,6 +21,9 @@ entries
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
+# coreboot config options: EC
+412 1 e 1 fan_full_speed
+
# coreboot config options: check sums
984 16 h 0 check_sum
diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
index c834fea5d3..6630a12e2a 100644
--- a/src/mainboard/dell/optiplex_9020/mainboard.c
+++ b/src/mainboard/dell/optiplex_9020/mainboard.c
@@ -1,7 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <bootstate.h>
+#include <cpu/x86/msr.h>
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
+#include <option.h>
+#include <southbridge/intel/common/gpio.h>
+#include "sch5555_ec.h"
static void mainboard_enable(struct device *dev)
{
@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev)
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
+
+#define HWM_TAB_ADD_TEMP_TARGET 1
+#define HWM_TAB_PKG_POWER_ANY 0xffff
+#define CHASSIS_TYPE_UNKNOWN 0xff
+
+struct hwm_tab_entry {
+ uint16_t addr;
+ uint8_t val;
+ uint8_t flags;
+ uint16_t pkg_power;
+};
+
+struct hwm_tab_entry HWM_TAB3[] = {
+ { 0x005, 0x33, 0, 0xffff },
+ { 0x018, 0x2f, 0, 0xffff },
+ { 0x019, 0x2f, 0, 0xffff },
+ { 0x01a, 0x2f, 0, 0xffff },
+ { 0x080, 0x00, 0, 0xffff },
+ { 0x081, 0x00, 0, 0xffff },
+ { 0x083, 0xbb, 0, 0xffff },
+ { 0x085, 0x8a, 0, 0x0010 },
+ { 0x086, 0x4c, 0, 0x0010 },
+ { 0x08a, 0x66, 0, 0x0010 },
+ { 0x08b, 0x5b, 0, 0x0010 },
+ { 0x090, 0x65, 0, 0xffff },
+ { 0x091, 0x70, 0, 0xffff },
+ { 0x092, 0x86, 0, 0xffff },
+ { 0x096, 0xa4, 0, 0xffff },
+ { 0x097, 0xa4, 0, 0xffff },
+ { 0x098, 0xa4, 0, 0xffff },
+ { 0x09b, 0xa4, 0, 0xffff },
+ { 0x0a0, 0x0e, 0, 0xffff },
+ { 0x0a1, 0x0e, 0, 0xffff },
+ { 0x0ae, 0x7c, 0, 0xffff },
+ { 0x0af, 0x86, 0, 0xffff },
+ { 0x0b0, 0x9a, 0, 0xffff },
+ { 0x0b3, 0x9a, 0, 0xffff },
+ { 0x0b6, 0x08, 0, 0xffff },
+ { 0x0b7, 0x08, 0, 0xffff },
+ { 0x0ea, 0x64, 0, 0x0020 },
+ { 0x0ea, 0x5c, 0, 0x0010 },
+ { 0x0ef, 0xff, 0, 0xffff },
+ { 0x0f8, 0x15, 0, 0xffff },
+ { 0x0f9, 0x00, 0, 0xffff },
+ { 0x0f0, 0x30, 0, 0xffff },
+ { 0x0fd, 0x01, 0, 0xffff },
+ { 0x1a1, 0x00, 0, 0xffff },
+ { 0x1a2, 0x00, 0, 0xffff },
+ { 0x1b1, 0x08, 0, 0xffff },
+ { 0x1be, 0x99, 0, 0xffff },
+ { 0x280, 0xa0, 0, 0x0010 },
+ { 0x281, 0x0f, 0, 0x0010 },
+ { 0x282, 0x03, 0, 0xffff },
+ { 0x283, 0x0a, 0, 0xffff },
+ { 0x284, 0x80, 0, 0xffff },
+ { 0x285, 0x03, 0, 0xffff },
+ { 0x288, 0x68, 0, 0x0010 },
+ { 0x289, 0x10, 0, 0x0010 },
+ { 0x28a, 0x03, 0, 0xffff },
+ { 0x28b, 0x0a, 0, 0xffff },
+ { 0x28c, 0x80, 0, 0xffff },
+ { 0x28d, 0x03, 0, 0xffff },
+};
+
+struct hwm_tab_entry HWM_TAB4[] = {
+ { 0x005, 0x33, 0, 0xffff },
+ { 0x018, 0x2f, 0, 0xffff },
+ { 0x019, 0x2f, 0, 0xffff },
+ { 0x01a, 0x2f, 0, 0xffff },
+ { 0x080, 0x00, 0, 0xffff },
+ { 0x081, 0x00, 0, 0xffff },
+ { 0x083, 0xbb, 0, 0xffff },
+ { 0x085, 0x99, 0, 0x0020 },
+ { 0x085, 0xad, 0, 0x0010 },
+ { 0x086, 0x1c, 0, 0xffff },
+ { 0x08a, 0x39, 0, 0x0020 },
+ { 0x08a, 0x41, 0, 0x0010 },
+ { 0x08b, 0x76, 0, 0x0020 },
+ { 0x08b, 0x8b, 0, 0x0010 },
+ { 0x090, 0x5e, 0, 0xffff },
+ { 0x091, 0x5e, 0, 0xffff },
+ { 0x092, 0x86, 0, 0xffff },
+ { 0x096, 0xa4, 0, 0xffff },
+ { 0x097, 0xa4, 0, 0xffff },
+ { 0x098, 0xa4, 0, 0xffff },
+ { 0x09b, 0xa4, 0, 0xffff },
+ { 0x0a0, 0x0a, 0, 0xffff },
+ { 0x0a1, 0x0a, 0, 0xffff },
+ { 0x0ae, 0x7c, 0, 0xffff },
+ { 0x0af, 0x7c, 0, 0xffff },
+ { 0x0b0, 0x9a, 0, 0xffff },
+ { 0x0b3, 0x7c, 0, 0xffff },
+ { 0x0b6, 0x08, 0, 0xffff },
+ { 0x0b7, 0x08, 0, 0xffff },
+ { 0x0ea, 0x64, 0, 0x0020 },
+ { 0x0ea, 0x5c, 0, 0x0010 },
+ { 0x0ef, 0xff, 0, 0xffff },
+ { 0x0f8, 0x15, 0, 0xffff },
+ { 0x0f9, 0x00, 0, 0xffff },
+ { 0x0f0, 0x30, 0, 0xffff },
+ { 0x0fd, 0x01, 0, 0xffff },
+ { 0x1a1, 0x00, 0, 0xffff },
+ { 0x1a2, 0x00, 0, 0xffff },
+ { 0x1b1, 0x08, 0, 0xffff },
+ { 0x1be, 0x90, 0, 0xffff },
+ { 0x280, 0x94, 0, 0x0020 },
+ { 0x281, 0x11, 0, 0x0020 },
+ { 0x280, 0x94, 0, 0x0010 },
+ { 0x281, 0x11, 0, 0x0010 },
+ { 0x282, 0x03, 0, 0xffff },
+ { 0x283, 0x0a, 0, 0xffff },
+ { 0x284, 0x80, 0, 0xffff },
+ { 0x285, 0x03, 0, 0xffff },
+ { 0x288, 0x28, 0, 0x0020 },
+ { 0x289, 0x0a, 0, 0x0020 },
+ { 0x288, 0x28, 0, 0x0010 },
+ { 0x289, 0x0a, 0, 0x0010 },
+ { 0x28a, 0x03, 0, 0xffff },
+ { 0x28b, 0x0a, 0, 0xffff },
+ { 0x28c, 0x80, 0, 0xffff },
+ { 0x28d, 0x03, 0, 0xffff },
+};
+
+struct hwm_tab_entry HWM_TAB5[] = {
+ { 0x005, 0x33, 0, 0xffff },
+ { 0x018, 0x2f, 0, 0xffff },
+ { 0x019, 0x2f, 0, 0xffff },
+ { 0x01a, 0x2f, 0, 0xffff },
+ { 0x080, 0x00, 0, 0xffff },
+ { 0x081, 0x00, 0, 0xffff },
+ { 0x083, 0xbb, 0, 0xffff },
+ { 0x085, 0x66, 0, 0x0020 },
+ { 0x085, 0x5d, 0, 0x0010 },
+ { 0x086, 0x1c, 0, 0xffff },
+ { 0x08a, 0x39, 0, 0x0020 },
+ { 0x08a, 0x41, 0, 0x0010 },
+ { 0x08b, 0x76, 0, 0x0020 },
+ { 0x08b, 0x80, 0, 0x0010 },
+ { 0x090, 0x5d, 0, 0x0020 },
+ { 0x090, 0x5e, 0, 0x0010 },
+ { 0x091, 0x5e, 0, 0xffff },
+ { 0x092, 0x86, 0, 0xffff },
+ { 0x096, 0xa4, 0, 0xffff },
+ { 0x097, 0xa4, 0, 0xffff },
+ { 0x098, 0xa3, 0, 0x0020 },
+ { 0x098, 0xa4, 0, 0x0010 },
+ { 0x09b, 0xa4, 0, 0xffff },
+ { 0x0a0, 0x08, 0, 0xffff },
+ { 0x0a1, 0x0a, 0, 0xffff },
+ { 0x0ae, 0x7c, 0, 0xffff },
+ { 0x0af, 0x7c, 0, 0xffff },
+ { 0x0b0, 0x9a, 0, 0xffff },
+ { 0x0b3, 0x7c, 0, 0xffff },
+ { 0x0b6, 0x08, 0, 0xffff },
+ { 0x0b7, 0x08, 0, 0xffff },
+ { 0x0ea, 0x64, 0, 0x0020 },
+ { 0x0ea, 0x5c, 0, 0x0010 },
+ { 0x0ef, 0xff, 0, 0xffff },
+ { 0x0f8, 0x15, 0, 0xffff },
+ { 0x0f9, 0x00, 0, 0xffff },
+ { 0x0f0, 0x30, 0, 0xffff },
+ { 0x0fd, 0x01, 0, 0xffff },
+ { 0x1a1, 0x00, 0, 0xffff },
+ { 0x1a2, 0x00, 0, 0xffff },
+ { 0x1b1, 0x08, 0, 0xffff },
+ { 0x1be, 0x98, 0, 0x0020 },
+ { 0x1be, 0x90, 0, 0x0010 },
+ { 0x280, 0x94, 0, 0x0020 },
+ { 0x281, 0x11, 0, 0x0020 },
+ { 0x280, 0x94, 0, 0x0010 },
+ { 0x281, 0x11, 0, 0x0010 },
+ { 0x282, 0x03, 0, 0xffff },
+ { 0x283, 0x0a, 0, 0xffff },
+ { 0x284, 0x80, 0, 0xffff },
+ { 0x285, 0x03, 0, 0xffff },
+ { 0x288, 0x28, 0, 0x0020 },
+ { 0x289, 0x0a, 0, 0x0020 },
+ { 0x288, 0x28, 0, 0x0010 },
+ { 0x289, 0x0a, 0, 0x0010 },
+ { 0x28a, 0x03, 0, 0xffff },
+ { 0x28b, 0x0a, 0, 0xffff },
+ { 0x28c, 0x80, 0, 0xffff },
+ { 0x28d, 0x03, 0, 0xffff },
+};
+
+struct hwm_tab_entry HWM_TAB6[] = {
+ { 0x005, 0x33, 0, 0xffff },
+ { 0x018, 0x2f, 0, 0xffff },
+ { 0x019, 0x2f, 0, 0xffff },
+ { 0x01a, 0x2f, 0, 0xffff },
+ { 0x080, 0x00, 0, 0xffff },
+ { 0x081, 0x00, 0, 0xffff },
+ { 0x083, 0xbb, 0, 0xffff },
+ { 0x085, 0x98, 0, 0xffff },
+ { 0x086, 0x3c, 0, 0xffff },
+ { 0x08a, 0x39, 0, 0x0020 },
+ { 0x08a, 0x3d, 0, 0x0010 },
+ { 0x08b, 0x44, 0, 0x0020 },
+ { 0x08b, 0x51, 0, 0x0010 },
+ { 0x090, 0x61, 0, 0xffff },
+ { 0x091, 0x6d, 0, 0xffff },
+ { 0x092, 0x86, 0, 0xffff },
+ { 0x096, 0xa4, 0, 0xffff },
+ { 0x097, 0xa4, 0, 0xffff },
+ { 0x098, 0x9f, 0, 0x0020 },
+ { 0x098, 0xa4, 0, 0x0010 },
+ { 0x09b, 0xa4, 0, 0xffff },
+ { 0x0a0, 0x0e, 0, 0xffff },
+ { 0x0a1, 0x0e, 0, 0xffff },
+ { 0x0ae, 0x7c, 0, 0xffff },
+ { 0x0af, 0x7c, 0, 0xffff },
+ { 0x0b0, 0x9b, 0, 0x0020 },
+ { 0x0b0, 0x98, 0, 0x0010 },
+ { 0x0b3, 0x9a, 0, 0xffff },
+ { 0x0b6, 0x08, 0, 0xffff },
+ { 0x0b7, 0x08, 0, 0xffff },
+ { 0x0ea, 0x64, 0, 0x0020 },
+ { 0x0ea, 0x5c, 0, 0x0010 },
+ { 0x0ef, 0xff, 0, 0xffff },
+ { 0x0f8, 0x15, 0, 0xffff },
+ { 0x0f9, 0x00, 0, 0xffff },
+ { 0x0f0, 0x30, 0, 0xffff },
+ { 0x0fd, 0x01, 0, 0xffff },
+ { 0x1a1, 0x00, 0, 0xffff },
+ { 0x1a2, 0x00, 0, 0xffff },
+ { 0x1b1, 0x08, 0, 0xffff },
+ { 0x1be, 0x9a, 0, 0x0020 },
+ { 0x1be, 0x96, 0, 0x0010 },
+ { 0x280, 0x94, 0, 0x0020 },
+ { 0x281, 0x11, 0, 0x0020 },
+ { 0x280, 0x94, 0, 0x0010 },
+ { 0x281, 0x11, 0, 0x0010 },
+ { 0x282, 0x03, 0, 0xffff },
+ { 0x283, 0x0a, 0, 0xffff },
+ { 0x284, 0x80, 0, 0xffff },
+ { 0x285, 0x03, 0, 0xffff },
+ { 0x288, 0x94, 0, 0x0020 },
+ { 0x289, 0x11, 0, 0x0020 },
+ { 0x288, 0x94, 0, 0x0010 },
+ { 0x289, 0x11, 0, 0x0010 },
+ { 0x28a, 0x03, 0, 0xffff },
+ { 0x28b, 0x0a, 0, 0xffff },
+ { 0x28c, 0x80, 0, 0xffff },
+ { 0x28d, 0x03, 0, 0xffff },
+};
+
+static uint8_t get_chassis_type(void)
+{
+ uint8_t gpio_chassis_type;
+
+ // Read chassis type from GPIO
+ gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 |
+ get_gpio(17) << 1 | get_gpio(1);
+
+ printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);
+
+ // Turn it into internal chassis index
+ switch (gpio_chassis_type) {
+ case 0x08:
+ case 0x0a:
+ return 4;
+ case 0x0b:
+ return 3;
+ case 0x0c:
+ return 5;
+ case 0x0d: // SFF
+ case 0x0e:
+ case 0x0f:
+ return 6;
+ default:
+ return CHASSIS_TYPE_UNKNOWN;
+ }
+
+}
+
+static uint8_t get_temp_target(void)
+{
+ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff;
+ if (!val)
+ val = 20;
+ return 0x95 - val;
+}
+
+static uint16_t get_pkg_power(void)
+{
+ uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf;
+ if (rapl_power_unit)
+ rapl_power_unit = 2 << (rapl_power_unit - 1);
+ uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff;
+ if (pkg_power_info / rapl_power_unit > 0x41)
+ return 32;
+ else
+ return 16;
+}
+
+static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size)
+{
+ uint8_t temp_target = get_temp_target();
+ uint16_t pkg_power = get_pkg_power();
+
+ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target);
+ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power);
+
+ for (size_t i = 0; i < size; ++i) {
+ // Skip entry if it doesn't apply for this package power
+ if (arr[i].pkg_power != pkg_power &&
+ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY)
+ continue;
+
+ uint8_t val = arr[i].val;
+
+ // Add temp target to value if requested (current tables never do)
+ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET)
+ val += temp_target;
+
+ // Perform write
+ sch5555_mbox_write(1, arr[i].addr, val);
+
+ }
+}
+
+static void sch5555_ec_hwm_init(void *arg)
+{
+ uint8_t chassis_type, saved_2fc;
+
+ printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n");
+
+ saved_2fc = sch5555_mbox_read(1, 0x2fc);
+ sch5555_mbox_write(1, 0x2fc, 0xa0);
+ sch5555_mbox_write(1, 0x2fd, 0x32);
+
+ chassis_type = get_chassis_type();
+
+ if (chassis_type != CHASSIS_TYPE_UNKNOWN) {
+ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type);
+ } else {
+ printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n");
+ }
+
+ // Apply HWM table based on chassis type
+ switch (chassis_type) {
+ case 3:
+ apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3));
+ break;
+ case 4:
+ apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4));
+ break;
+ case 5:
+ apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5));
+ break;
+ case 6:
+ apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6));
+ break;
+ }
+
+ // NOTE: vendor firmware applies these when "max core address" > 2
+ // i think this is always the case
+ sch5555_mbox_write(1, 0x9e, 0x30);
+ sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea));
+
+ sch5555_mbox_write(1, 0x2fc, saved_2fc);
+
+ // Apply full speed fan config if requested or if the chassis type is unknown
+ if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) {
+ printk(BIOS_DEBUG, "Setting full fan speed\n");
+ sch5555_mbox_write(1, 0x80, 0x60 | sch5555_mbox_read(1, 0x80));
+ sch5555_mbox_write(1, 0x81, 0x60 | sch5555_mbox_read(1, 0x81));
+ }
+
+ sch5555_mbox_read(1, 0xb8);
+
+ if ((chassis_type == 4 || chassis_type == 5) && sch5555_mbox_read(1, 0x26) == 0) {
+ sch5555_mbox_write(1, 0xa0, sch5555_mbox_read(1, 0xa0) & 0xfb);
+ sch5555_mbox_write(1, 0xa1, sch5555_mbox_read(1, 0xa1) & 0xfb);
+ sch5555_mbox_write(1, 0xa2, sch5555_mbox_read(1, 0xa2) & 0xfb);
+ sch5555_mbox_write(1, 0x8a, 0x99);
+ sch5555_mbox_write(1, 0x8b, 0x47);
+ sch5555_mbox_write(1, 0x8c, 0x91);
+ }
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL);
diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
new file mode 100644
index 0000000000..1df5026531
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <device/pnp_ops.h>
+#include <superio/smsc/sch555x/sch555x.h>
+#include "sch5555_ec.h"
+
+uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2)
+{
+ // clear ec-to-host mailbox
+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
+ outb(tmp, SCH555x_EMI_IOBASE + 1);
+
+ // send address
+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
+ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4);
+
+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
+ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4);
+
+ // send message to ec
+ outb(1, SCH555x_EMI_IOBASE);
+
+ // wait for ack
+ for (size_t retry = 0; retry < 0xfff; ++retry)
+ if (inb(SCH555x_EMI_IOBASE + 1) & 1)
+ break;
+
+ // read result
+ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2);
+ return inb(SCH555x_EMI_IOBASE + 4);
+}
+
+void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val)
+{
+ // clear ec-to-host mailbox
+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
+ outb(tmp, SCH555x_EMI_IOBASE + 1);
+
+ // send address and value
+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
+ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4);
+
+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
+ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4);
+
+ // send message to ec
+ outb(1, SCH555x_EMI_IOBASE);
+
+ // wait for ack
+ for (size_t retry = 0; retry < 0xfff; ++retry)
+ if (inb(SCH555x_EMI_IOBASE + 1) & 1)
+ break;
+}
diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
new file mode 100644
index 0000000000..9d262d5787
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SCH5555_EC_H__
+#define __SCH5555_EC_H__
+
+uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2);
+
+void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val);
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 03:48:45 +0000