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-rw-r--r--src/mainboard/broadcom/Kconfig2
-rw-r--r--src/mainboard/broadcom/blast/devicetree.cb6
-rw-r--r--src/mainboard/broadcom/blast/get_bus_conf.c8
-rw-r--r--src/mainboard/broadcom/blast/irq_tables.c18
-rw-r--r--src/mainboard/broadcom/blast/mptable.c18
-rw-r--r--src/mainboard/broadcom/blast/resourcemap.c14
-rw-r--r--src/mainboard/broadcom/blast/romstage.c12
7 files changed, 39 insertions, 39 deletions
diff --git a/src/mainboard/broadcom/Kconfig b/src/mainboard/broadcom/Kconfig
index bf956ecdb3..d7406c0b45 100644
--- a/src/mainboard/broadcom/Kconfig
+++ b/src/mainboard/broadcom/Kconfig
@@ -1,7 +1,7 @@
choice
prompt "Mainboard model"
depends on VENDOR_BROADCOM
-
+
source "src/mainboard/broadcom/blast/Kconfig"
endchoice
diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb
index a9cabe6bea..d06c590bf8 100644
--- a/src/mainboard/broadcom/blast/devicetree.cb
+++ b/src/mainboard/broadcom/blast/devicetree.cb
@@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex
end
device pci_domain 0 on
chip northbridge/amd/amdk8
- device pci 18.0 on # northbridge
+ device pci 18.0 on # northbridge
# devices on link 0
chip southbridge/broadcom/bcm5780 # HT2000
device pci 0.0 on end # PXB 1 0x0130
@@ -95,7 +95,7 @@ chip northbridge/amd/amdk8/root_complex
device pnp 2e.10 on #RTC
io 0x60 = 0x70
io 0x62 = 0x72
- end
+ end
end
end
device pci 1.3 on end # WDTimer 0x0238
@@ -110,7 +110,7 @@ chip northbridge/amd/amdk8/root_complex
end # device pci 18.0
device pci 18.0 on end
- device pci 18.0 on end
+ device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c
index 9d1a4b1bf0..06f42f4092 100644
--- a/src/mainboard/broadcom/blast/get_bus_conf.c
+++ b/src/mainboard/broadcom/blast/get_bus_conf.c
@@ -21,7 +21,7 @@ unsigned char bus_bcm5785_1_1 = 9;
unsigned apicid_bcm5785[3];
-unsigned pci1234x[] =
+unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
@@ -115,9 +115,9 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(3);
-#else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#else
+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
- for(i=0;i<3;i++)
+ for(i=0;i<3;i++)
apicid_bcm5785[i] = apicid_base+i;
}
diff --git a/src/mainboard/broadcom/blast/irq_tables.c b/src/mainboard/broadcom/blast/irq_tables.c
index 3f6f73893e..406419d6d8 100644
--- a/src/mainboard/broadcom/blast/irq_tables.c
+++ b/src/mainboard/broadcom/blast/irq_tables.c
@@ -1,4 +1,4 @@
-/* This file was generated by getpir.c, do not modify!
+/* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
@@ -16,7 +16,7 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu)
{
- pirq_info->bus = bus;
+ pirq_info->bus = bus;
pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0;
@@ -64,22 +64,22 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq = (void *)(addr);
v = (uint8_t *)(addr);
-
+
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
-
+
pirq->rtr_bus = bus_bcm5785_0;
pirq->rtr_devfn = (sysconf.sbdn<<3)|0;
pirq->exclusive_irqs = 0;
-
+
pirq->rtr_vendor = 0x1166;
pirq->rtr_device = 0x0036;
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
+
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
pirq_info = (void *) ( &pirq->checksum + 1);
@@ -87,11 +87,11 @@ unsigned long write_pirq_routing_table(unsigned long addr)
//pci bridge
write_pirq_info(pirq_info, bus_bcm5785_0, (sysconf.sbdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
+
+ pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
- sum += v[i];
+ sum += v[i];
sum = pirq->checksum - sum;
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index 8a1b133bfb..d24630844e 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -72,12 +72,12 @@ static void *smp_write_config_table(void *v)
}
}
}
-
+
}
-
+
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_bcm5785[0], 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_bcm5785[0], 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_bcm5785[0], 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_bcm5785[0], 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_bcm5785[0], 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_bcm5785[0], 0x4);
@@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_bcm5785[0], 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_bcm5785[0], 0xd);
-//IDE
+//IDE
outb(0x02, 0xc00); outb(0x0e, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE
@@ -97,14 +97,14 @@ static void *smp_write_config_table(void *v)
//SATA
outb(0x07, 0xc00); outb(0x0f, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf);
-
+
//USB
outb(0x01, 0xc00); outb(0x0a, 0xc01);
for(i=0;i<3;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
}
-
+
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
@@ -127,13 +127,13 @@ static void *smp_write_config_table(void *v)
}
-//pci slot (on bcm5785)
+//pci slot (on bcm5785)
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); //
}
-//onboard ati
+//onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1);
//PCI-X on bcm5780
@@ -157,7 +157,7 @@ static void *smp_write_config_table(void *v)
}
-// Second PCI-E x8
+// Second PCI-E x8
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); //
}
diff --git a/src/mainboard/broadcom/blast/resourcemap.c b/src/mainboard/broadcom/blast/resourcemap.c
index 438605c701..71f0bba010 100644
--- a/src/mainboard/broadcom/blast/resourcemap.c
+++ b/src/mainboard/broadcom/blast/resourcemap.c
@@ -119,7 +119,7 @@ static void setup_blast_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
+ PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -144,7 +144,7 @@ static void setup_blast_resource_map(void)
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
+ * This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -181,7 +181,7 @@ static void setup_blast_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -200,7 +200,7 @@ static void setup_blast_resource_map(void)
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
+ * 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
@@ -208,7 +208,7 @@ static void setup_blast_resource_map(void)
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
+ * This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
@@ -252,8 +252,8 @@ static void setup_blast_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
+ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};
diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index 35823bd47c..13f5f97414 100644
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -3,7 +3,7 @@
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
-
+
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -75,7 +75,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "lib/generic_sdram.c"
/* tyan does not want the default */
-#include "resourcemap.c"
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
@@ -109,7 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct mem_controller ctrl[8];
unsigned nodes;
- if (!cpu_init_detectedx && boot_cpu()) {
+ if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
@@ -130,7 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
// post_code(0x33);
-
+
uart_init();
// post_code(0x34);
@@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
setup_blast_resource_map();
-
+
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
@@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
-#if 0
+#if 0
int i;
for(i=4;i<8;i++) {
change_i2c_mux(i);
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-17 17:50:06 +0000