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-rw-r--r--src/mainboard/biostar/th61-itx/Kconfig33
-rw-r--r--src/mainboard/biostar/th61-itx/Kconfig.name2
-rw-r--r--src/mainboard/biostar/th61-itx/Makefile.inc7
-rw-r--r--src/mainboard/biostar/th61-itx/acpi/ec.asl0
-rw-r--r--src/mainboard/biostar/th61-itx/acpi/platform.asl16
-rw-r--r--src/mainboard/biostar/th61-itx/acpi/superio.asl0
-rw-r--r--src/mainboard/biostar/th61-itx/acpi_tables.c8
-rw-r--r--src/mainboard/biostar/th61-itx/board_info.txt6
-rw-r--r--src/mainboard/biostar/th61-itx/cmos.default6
-rw-r--r--src/mainboard/biostar/th61-itx/cmos.layout66
-rw-r--r--src/mainboard/biostar/th61-itx/data.vbtbin0 -> 3777 bytes
-rw-r--r--src/mainboard/biostar/th61-itx/devicetree.cb79
-rw-r--r--src/mainboard/biostar/th61-itx/dsdt.asl27
-rw-r--r--src/mainboard/biostar/th61-itx/early_init.c29
-rw-r--r--src/mainboard/biostar/th61-itx/gma-mainboard.ads18
-rw-r--r--src/mainboard/biostar/th61-itx/gpio.c181
-rw-r--r--src/mainboard/biostar/th61-itx/hda_verb.c28
17 files changed, 506 insertions, 0 deletions
diff --git a/src/mainboard/biostar/th61-itx/Kconfig b/src/mainboard/biostar/th61-itx/Kconfig
new file mode 100644
index 0000000000..2719853449
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/Kconfig
@@ -0,0 +1,33 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_BIOSTAR_TH61_ITX
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_4096
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select USE_NATIVE_RAMINIT
+ select SUPERIO_ITE_IT8728F
+ select MAINBOARD_HAS_LIBGFXINIT
+ select INTEL_GMA_HAVE_VBT
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select NO_UART_ON_SUPERIO
+
+config MAINBOARD_DIR
+ string
+ default "biostar/th61-itx"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "TH61-ITX"
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 2
+
+endif # BOARD_BIOSTAR_TH61_ITX
diff --git a/src/mainboard/biostar/th61-itx/Kconfig.name b/src/mainboard/biostar/th61-itx/Kconfig.name
new file mode 100644
index 0000000000..fecf255b81
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_BIOSTAR_TH61_ITX
+ bool "TH61-ITX"
diff --git a/src/mainboard/biostar/th61-itx/Makefile.inc b/src/mainboard/biostar/th61-itx/Makefile.inc
new file mode 100644
index 0000000000..549a84fd12
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/Makefile.inc
@@ -0,0 +1,7 @@
+bootblock-y += gpio.c
+romstage-y += gpio.c
+
+ramstage-y += hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c
diff --git a/src/mainboard/biostar/th61-itx/acpi/ec.asl b/src/mainboard/biostar/th61-itx/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/acpi/ec.asl
diff --git a/src/mainboard/biostar/th61-itx/acpi/platform.asl b/src/mainboard/biostar/th61-itx/acpi/platform.asl
new file mode 100644
index 0000000000..bbee0a2787
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/acpi/platform.asl
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/biostar/th61-itx/acpi/superio.asl b/src/mainboard/biostar/th61-itx/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/acpi/superio.asl
diff --git a/src/mainboard/biostar/th61-itx/acpi_tables.c b/src/mainboard/biostar/th61-itx/acpi_tables.c
new file mode 100644
index 0000000000..852b0b4ae7
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/acpi_tables.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(struct global_nvs *gnvs)
+{
+}
diff --git a/src/mainboard/biostar/th61-itx/board_info.txt b/src/mainboard/biostar/th61-itx/board_info.txt
new file mode 100644
index 0000000000..4832134217
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: http://biostar-usa.com/app/en-us/mb/introduction.php?S_ID=548
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/biostar/th61-itx/cmos.default b/src/mainboard/biostar/th61-itx/cmos.default
new file mode 100644
index 0000000000..6f3cec735e
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Enable
+nmi=Enable
+sata_mode=AHCI
+gfx_uma_size=32M
diff --git a/src/mainboard/biostar/th61-itx/cmos.layout b/src/mainboard/biostar/th61-itx/cmos.layout
new file mode 100644
index 0000000000..556b34e29d
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/cmos.layout
@@ -0,0 +1,66 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+
+# coreboot config options: console
+395 4 e 6 debug_level
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+421 1 e 9 sata_mode
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 IDE
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 439 984
diff --git a/src/mainboard/biostar/th61-itx/data.vbt b/src/mainboard/biostar/th61-itx/data.vbt
new file mode 100644
index 0000000000..f2ec2fcfb0
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/data.vbt
Binary files differ
diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb
new file mode 100644
index 0000000000..2329bb23e3
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/devicetree.cb
@@ -0,0 +1,79 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+ device cpu_cluster 0 on
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+ end
+ register "pci_mmio_size" = "2048"
+ device domain 0 on
+ subsystemid 0x1565 0x3108 inherit
+
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PEG
+ device pci 02.0 on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "gen1_dec" = "0x003c0a01"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device pci 16.0 on end # MEI #1
+ device pci 1a.0 on end # EHCI #2
+ device pci 1b.0 on end # HD Audio
+ device pci 1c.0 on end # RP #1: Realtek RTL8111F GbE NIC
+ device pci 1c.1 on end # RP #2: ASMedia ASM1042 USB3 #1
+ device pci 1c.2 on end # RP #3: ASMedia ASM1042 USB3 #2
+ device pci 1c.3 off end # RP #4
+ device pci 1c.4 off end # RP #5
+ device pci 1c.5 off end # RP #6
+ device pci 1d.0 on end # EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/ite/it8728f
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 off end # COM1
+ device pnp 2e.2 off end # COM2
+ device pnp 2e.3 off end # Parallel port
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0x0a30
+ io 0x62 = 0x0a20
+ end
+ device pnp 2e.5 on end # Keyboard
+ device pnp 2e.6 on end # Mouse
+ device pnp 2e.7 on # GPIO
+ irq 0x26 = 0xff
+ irq 0x27 = 0x30
+ irq 0x28 = 0x80
+ irq 0x29 = 0x80
+ irq 0x2c = 0x02
+ io 0x60 = 0x0a10
+ io 0x62 = 0x0a00
+ irq 0xb1 = 0x03
+ irq 0xb3 = 0x80
+ irq 0xb8 = 0x00
+ irq 0xf5 = 0x27
+ irq 0xf8 = 0x20
+ irq 0xf9 = 0x01
+ end
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device pci 1f.2 on end # SATA #1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA #2 (IDE mode)
+ device pci 1f.6 on end # Thermal subsystem
+ end
+ end
+end
diff --git a/src/mainboard/biostar/th61-itx/dsdt.asl b/src/mainboard/biostar/th61-itx/dsdt.asl
new file mode 100644
index 0000000000..18908d38a7
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/biostar/th61-itx/early_init.c b/src/mainboard/biostar/th61-itx/early_init.c
new file mode 100644
index 0000000000..b1a99e0ee8
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/early_init.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/biostar/th61-itx/gma-mainboard.ads b/src/mainboard/biostar/th61-itx/gma-mainboard.ads
new file mode 100644
index 0000000000..81097a67f7
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/gma-mainboard.ads
@@ -0,0 +1,18 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+ -- TODO: verify this with a CPU that has an IGP
+ ports : constant Port_List :=
+ (HDMI1, -- DVI
+ HDMI2, -- HDMI
+ HDMI3,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/biostar/th61-itx/gpio.c b/src/mainboard/biostar/th61-itx/gpio.c
new file mode 100644
index 0000000000..3628678c7d
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/gpio.c
@@ -0,0 +1,181 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_NATIVE,
+ .gpio22 = GPIO_MODE_NATIVE,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_NATIVE,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {};
+
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/biostar/th61-itx/hda_verb.c b/src/mainboard/biostar/th61-itx/hda_verb.c
new file mode 100644
index 0000000000..2b6d27604d
--- /dev/null
+++ b/src/mainboard/biostar/th61-itx/hda_verb.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0892, /* Realtek ALC892 */
+ 0x15658229, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(2, 0x15658229),
+ AZALIA_PIN_CFG(2, 0x11, 0x01452130),
+ AZALIA_PIN_CFG(2, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(2, 0x14, 0x01014410),
+ AZALIA_PIN_CFG(2, 0x15, 0x01011412),
+ AZALIA_PIN_CFG(2, 0x16, 0x01016411),
+ AZALIA_PIN_CFG(2, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(2, 0x18, 0x01a19c40),
+ AZALIA_PIN_CFG(2, 0x19, 0x02a19850),
+ AZALIA_PIN_CFG(2, 0x1a, 0x0181344f),
+ AZALIA_PIN_CFG(2, 0x1b, 0x02214020),
+ AZALIA_PIN_CFG(2, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(2, 0x1d, 0x4005e601),
+ AZALIA_PIN_CFG(2, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(2, 0x1f, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 08:28:22 +0000