4 files changed, 7 insertions, 29 deletions
diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb
index 972dc5dc1f..b5409a25bb 100644
--- a/src/mainboard/asus/p5gc-mx/devicetree.cb
+++ b/src/mainboard/asus/p5gc-mx/devicetree.cb
@@ -55,6 +55,9 @@ chip northbridge/intel/i945
 
 			register "p_cnt_throttling_supported" = "0"
 
+			# SuperIO Power Management Events
+			register "gen1_dec" = "0x00040291"
+
 			device pci 1b.0 on # High Definition Audio
 				ioapic_irq 2 INTA 0x10
 			end
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 58dac6e71c..3287b76416 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -96,20 +96,6 @@ static u8 msr_get_fsb(void)
 	return fsbcfg;
 }
 
-static void ich7_enable_lpc(void)
-{
-	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
-	// Set COM1/COM2 decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
-	// Enable COM1
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
-			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
-			| COMA_LPC_EN);
-	// Enable SuperIO Power Management Events
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00040291);
-}
-
 static void rcba_config(void)
 {
 	/* Enable IOAPIC */
@@ -156,7 +142,7 @@ void mainboard_romstage_entry(void)
 
 	enable_lapic();
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb
index bc023d24c9..5012f88605 100644
--- a/src/mainboard/asus/p5qpl-am/devicetree.cb
+++ b/src/mainboard/asus/p5qpl-am/devicetree.cb
@@ -45,6 +45,8 @@ chip northbridge/intel/x4x		# Northbridge
 			register "ide_enable_primary" = "0x1"
 			register "gpe0_en" = "0x04000440"
 
+			register "gen1_dec" = "0x00000295" # HWM
+
 			device pci 1b.0 on  end		# Audio
 			device pci 1c.0 on  end		# PCIe 1: PCIe x1 slot
 			device pci 1c.1 on		# PCIe 2: NIC
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index 2836bf7941..4653b42267 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -143,19 +143,6 @@ static void mb_lpc_setup(void)
 	ich7_setup_cir();
 }
 
-static void ich7_enable_lpc(void)
-{
-	pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
-	/* Fixed IO decode ranges */
-	pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
-	/* LPC enable devices */
-	pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
-			   | FDD_LPC_EN | LPT_LPC_EN
-			   | COMB_LPC_EN |  COMA_LPC_EN);
-	/* IO decode range: HWM on 0x295 */
-	pci_write_config32(LPC_DEV, 0x84, 0x000295);
-}
-
 void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
@@ -164,7 +151,7 @@ void mainboard_romstage_entry(void)
 	u8 s3_resume;
 
 	/* Set southbridge and Super I/O GPIOs. */
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	mb_lpc_setup();
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);