diff options
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r-- | src/mainboard/asus/kfsn4-dre/romstage.c | 9 | ||||
-rw-r--r-- | src/mainboard/asus/m4a78-em/romstage.c | 9 | ||||
-rw-r--r-- | src/mainboard/asus/m4a785-m/romstage.c | 9 | ||||
-rw-r--r-- | src/mainboard/asus/m5a88-v/romstage.c | 9 |
4 files changed, 36 insertions, 0 deletions
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 44864f6dd8..af6858f000 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -35,6 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> +#include <timestamp.h> #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> @@ -213,6 +214,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0, val, wants_reset; msr_t msr; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -341,8 +345,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + timestamp_add_now(TS_AFTER_INITRAM); + cbmem_initialize_empty(); post_code(0x41); @@ -368,6 +375,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Restore default SuperIO access */ outb(0xaa, port); + timestamp_add_now(TS_END_ROMSTAGE); + post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 47b9c834bf..da63c661de 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -33,6 +33,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> +#include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> @@ -78,6 +79,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0, val; msr_t msr; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -200,8 +204,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("Die Before MCT init."); + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + timestamp_add_now(TS_AFTER_INITRAM); + cbmem_initialize_empty(); post_code(0x41); @@ -217,6 +224,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); + timestamp_add_now(TS_END_ROMSTAGE); + post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 7ebec29a7f..e0c132fc40 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -33,6 +33,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> +#include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> @@ -78,6 +79,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0, val; msr_t msr; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -200,8 +204,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("Die Before MCT init."); + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + timestamp_add_now(TS_AFTER_INITRAM); + cbmem_initialize_empty(); post_code(0x41); @@ -217,6 +224,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); + timestamp_add_now(TS_END_ROMSTAGE); + post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 23394789bb..cc4d04dd8d 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -34,6 +34,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> +#include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> @@ -78,6 +79,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0, val; msr_t msr; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -195,8 +199,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("Die Before MCT init."); + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + timestamp_add_now(TS_AFTER_INITRAM); + cbmem_initialize_empty(); post_code(0x41); @@ -214,6 +221,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_before_pci_init(); + timestamp_add_now(TS_END_ROMSTAGE); + post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. |