diff options
Diffstat (limited to 'src/mainboard/asus/p5ql-em')
| -rw-r--r-- | src/mainboard/asus/p5ql-em/romstage.c | 51 |
1 files changed, 15 insertions, 36 deletions
diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c index c7ade1c541..fa22a645d4 100644 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -12,22 +12,22 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <device/pnp_ops.h> #include <console/console.h> -#include <southbridge/intel/i82801jx/i82801jx.h> -#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> -#include <arch/romstage.h> #include <cf9_reset.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/common/winbond.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void mb_lpc_setup(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} static u8 msr_get_fsb(void) { @@ -103,41 +103,20 @@ static int setup_sio_gpio(void) return need_reset; } -void mainboard_romstage_entry(void) +void mb_pre_raminit_setup(int s3_resume) { - /* This board has first dimm slot of each channel hooked up to - rank0 and rank1, while the second dimm slot is only connected - to rank1. The raminit does not support such setups - const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */ - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801jx_lpc_setup(); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801jx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - if (!s3_resume && setup_sio_gpio()) { printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); full_reset(); } +} - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); +void mb_get_spd_map(u8 spd_map[4]) +{ + /* This board has first dimm slot of each channel hooked up to + rank0 and rank1, while the second dimm slot is only connected + to rank1. The raminit does not support such setups. So only the + first dimms of each channel are used. */ + spd_map[0] = 0x50; + spd_map[2] = 0x52; } |