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Diffstat (limited to 'src/mainboard/asus/f2a85-m/acpi/routing.asl')
-rw-r--r--src/mainboard/asus/f2a85-m/acpi/routing.asl110
1 files changed, 78 insertions, 32 deletions
diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl
index b939b6addb..0685f8d752 100644
--- a/src/mainboard/asus/f2a85-m/acpi/routing.asl
+++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,16 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
- )
- {
- #include "routing.asl"
- }
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
+ /* Routing is in System Bus scope */
Name(PR0, Package(){
/* NB devices */
/* Bus 0, Dev 0 - F15 Host Controller */
@@ -45,24 +37,27 @@ Scope(\_SB) {
Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 },
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
/* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
Package(){0x0004FFFF, 0, INTA, 0 },
Package(){0x0004FFFF, 1, INTB, 0 },
Package(){0x0004FFFF, 2, INTC, 0 },
Package(){0x0004FFFF, 3, INTD, 0 },
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices */
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
Package(){0x0014FFFF, 0, INTA, 0 },
Package(){0x0014FFFF, 1, INTB, 0 },
Package(){0x0014FFFF, 2, INTC, 0 },
Package(){0x0014FFFF, 3, INTD, 0 },
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
Package(){0x0012FFFF, 0, INTC, 0 },
Package(){0x0012FFFF, 1, INTB, 0 },
@@ -72,7 +67,8 @@ Scope(\_SB) {
Package(){0x0016FFFF, 0, INTC, 0 },
Package(){0x0016FFFF, 1, INTB, 0 },
- /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ /* SB devices */
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
Package(){0x0010FFFF, 0, INTC, 0 },
Package(){0x0010FFFF, 1, INTB, 0 },
@@ -104,23 +100,28 @@ Scope(\_SB) {
Package(){0x0002FFFF, 2, 0, 16 },
Package(){0x0002FFFF, 3, 0, 17 },
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
/* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
Package(){0x0004FFFF, 0, 0, 16 },
Package(){0x0004FFFF, 1, 0, 17 },
Package(){0x0004FFFF, 2, 0, 18 },
Package(){0x0004FFFF, 3, 0, 19 },
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
- /* SB devices in APIC mode */
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
Package(){0x0014FFFF, 0, 0, 16 },
Package(){0x0014FFFF, 1, 0, 17 },
Package(){0x0014FFFF, 2, 0, 18 },
Package(){0x0014FFFF, 3, 0, 19 },
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
Package(){0x0012FFFF, 0, 0, 18 },
Package(){0x0012FFFF, 1, 0, 17 },
@@ -130,7 +131,7 @@ Scope(\_SB) {
Package(){0x0016FFFF, 0, 0, 18 },
Package(){0x0016FFFF, 1, 0, 17 },
- /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
Package(){0x0010FFFF, 0, 0, 0x12},
Package(){0x0010FFFF, 1, 0, 0x11},
@@ -153,26 +154,72 @@ Scope(\_SB) {
})
Name(APS2, Package(){
/* The external GFX - Hooked to PCIe slot 2 */
- Package(){0x0000FFFF, 0, 0, 0x12 },
- Package(){0x0000FFFF, 1, 0, 0x13 },
- Package(){0x0000FFFF, 2, 0, 0x10 },
- Package(){0x0000FFFF, 3, 0, 0x11 },
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
})
/* black slot */
Name(PS4, Package(){
- /* PCIe slot - Hooked to PCIe slot x4 */
+ /* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(APS4, Package(){
- /* PCIe slot - Hooked to PCIe slot x4 */
- Package(){0x0000FFFF, 0, 0, 0x10 },
- Package(){0x0000FFFF, 1, 0, 0x11 },
- Package(){0x0000FFFF, 2, 0, 0x12 },
- Package(){0x0000FFFF, 3, 0, 0x13 },
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
})
Name(PBR0, Package(){
@@ -213,4 +260,3 @@ Scope(\_SB) {
Package(){0x0005FFFF, 2, 0, 0x16 },
Package(){0x0005FFFF, 3, 0, 0x17 },
})
-}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-15 20:48:50 +0000