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-rw-r--r--src/mainboard/arima/hdama/Config.lb123
-rw-r--r--src/mainboard/arima/hdama/Options.lb10
-rw-r--r--src/mainboard/arima/hdama/auto.c51
-rw-r--r--src/mainboard/arima/hdama/debug.c143
-rw-r--r--src/mainboard/arima/hdama/mptable.c52
-rw-r--r--src/mainboard/arima/hdama/reset.c6
6 files changed, 335 insertions, 50 deletions
diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb
index a9df17bcdf..0b04d51214 100644
--- a/src/mainboard/arima/hdama/Config.lb
+++ b/src/mainboard/arima/hdama/Config.lb
@@ -29,7 +29,7 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
-default XIP_ROM_SIZE=65536
+default XIP_ROM_SIZE=131072
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
@@ -45,13 +45,13 @@ arch i386 end
driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
+object reset.o
##
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ./romcc"
+ depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
@@ -60,11 +60,11 @@ makerule ./failover.inc
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
-makerule ./auto.inc
+makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
@@ -129,61 +129,122 @@ config chip.h
# config for arima/hdama
chip northbridge/amd/amdk8/root_complex
- device apic_cluster 0 on
- chip cpu/amd/socket_940
- device apic 0 on end
- end
- chip cpu/amd/socket_940
- device apic 1 on end
- end
- end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
- device pci 0.0 on end # PCIX bridge
+ device pci 0.0 on # PCIX bridge
+ ## On board NIC A
+ #chip drivers/generic/generic
+ # device pci 3.0 on
+ # irq 0 = 0x13
+ # end
+ #end
+ ## On board NIC B
+ #chip drivers/generic/generic
+ # device pci 4.0 on
+ # irq 0 = 0x13
+ # end
+ #end
+ ## PCI Slot 3
+ #chip drivers/generic/generic
+ # device pci 1.0 on
+ # irq 0 = 0x11
+ # irq 1 = 0x12
+ # irq 2 = 0x13
+ # irq 3 = 0x10
+ # end
+ #end
+ ## PCI Slot 4
+ #chip drivers/generic/generic
+ # device pci 2.0 on
+ # irq 0 = 0x12
+ # irq 1 = 0x13
+ # irq 2 = 0x10
+ # irq 3 = 0x11
+ # end
+ #end
+ end
device pci 0.1 on end # IOAPIC
- device pci 1.0 on end # PCIX bridge
- device pci 1.1 on end # IOAPIC
+ device pci 1.0 on # PCIX bridge
+ ## PCI Slot 1
+ #chip drivers/generic/generic
+ # device pci 1.0 on
+ # irq 0 = 0x11
+ # irq 1 = 0x12
+ # irq 2 = 0x13
+ # irq 3 = 0x10
+ # end
+ #end
+ ## PCI Slot 2
+ #chip drivers/generic/generic
+ # device pci 2.0 on
+ # irq 0 = 0x12
+ # irq 1 = 0x13
+ # irq 2 = 0x10
+ # irq 3 = 0x11
+ # end
+ #end
+ end
+ device pci 1.1 on end # IOAPIC
end
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent of the next one
# PCI bridge
device pci 0.0 on
- device pci 0.0 on end # USB0
- device pci 0.1 on end # USB1
- device pci 0.2 off end # USB 2.0
- device pci 1.0 off end # LAN
+ device pci 0.0 on end # USB0
+ device pci 0.1 on end # USB1
+ device pci 0.2 off end # USB 2.0
+ device pci 1.0 off end # LAN
chip drivers/pci/onboard
device pci 6.0 on end # ATI Rage XL
register "rom_address" = "0xfff80000"
end
+ ## PCI Slot 5 (correct?)
+ #chip drivers/generic/generic
+ # device pci 5.0 on
+ # irq 0 = 0x11
+ # irq 1 = 0x12
+ # irq 2 = 0x13
+ # irq 3 = 0x10
+ # end
+ #end
+ ## PCI Slot 6 (correct?)
+ #chip drivers/generic/generic
+ # device pci 4.0 on
+ # irq 0 = 0x10
+ # irq 1 = 0x11
+ # irq 2 = 0x12
+ # irq 3 = 0x13
+ # end
+ #end
+
end
# LPC bridge
device pci 1.0 on
chip superio/NSC/pc87360
- device pnp 2e.0 off # Floppy
+ device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
- device pnp 2e.1 off # Parallel Port
+ device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
- device pnp 2e.2 off # Com 2
+ device pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
end
- device pnp 2e.3 on # Com 1
+ device pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.4 off end # SWC
device pnp 2e.5 off end # Mouse
- device pnp 2e.6 on # Keyboard
+ device pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
@@ -239,7 +300,7 @@ chip northbridge/amd/amdk8/root_complex
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
- end # device pci 18.0
+ end # device pci 18.0
device pci 18.0 on end # LDT1
device pci 18.0 on end # LDT2
@@ -255,6 +316,14 @@ chip northbridge/amd/amdk8/root_complex
device pci 19.2 on end
device pci 19.3 on end
end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
end
end
diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb
index 773d698ad2..9d70f5b7ef 100644
--- a/src/mainboard/arima/hdama/Options.lb
+++ b/src/mainboard/arima/hdama/Options.lb
@@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
@@ -80,13 +77,6 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_HARD_RESET=1
##
-## Funky hard reset implementation
-##
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
-##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
diff --git a/src/mainboard/arima/hdama/auto.c b/src/mainboard/arima/hdama/auto.c
index b4d955385f..7790b3ea50 100644
--- a/src/mainboard/arima/hdama/auto.c
+++ b/src/mainboard/arima/hdama/auto.c
@@ -11,6 +11,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
+#include "northbridge/amd/amdk8/cpu_rev.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
@@ -18,28 +19,59 @@
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87360/pc87360_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
+/* Look up a which bus a given node/link combination is on.
+ * return 0 when we can't find the answer.
+ */
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+ unsigned reg;
+
+ for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+ unsigned config_map;
+ config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
+ if ((config_map & 3) != 3) {
+ continue;
+ }
+ if ((((config_map >> 4) & 7) == node) &&
+ (((config_map >> 8) & 3) == link))
+ {
+ return (config_map >> 16) & 0xff;
+ }
+ }
+ return 0;
+}
+
static void hard_reset(void)
{
- set_bios_reset();
+ device_t dev;
+ /* Find the device */
+ dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
+
/* enable cf9 */
- pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+ pci_write_config8(dev, 0x41, 0xf1);
+
/* reset */
+ set_bios_reset();
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
+ device_t dev;
+
+ /* Find the device */
+ dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
+
+ /* Reset */
set_bios_reset();
- pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+ pci_write_config8(dev, 0x47, 1);
}
/*
@@ -128,6 +160,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
+#include "debug.c"
#define FIRST_CPU 1
#define SECOND_CPU 1
@@ -160,13 +193,14 @@ static void main(unsigned long bist)
};
int needs_reset;
- unsigned nodeid;
if (bist == 0) {
+ unsigned nodeid;
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
enable_lapic();
init_timer();
nodeid = lapicid() & 0xf;
+
/* Has this cpu already booted? */
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
@@ -191,13 +225,12 @@ static void main(unsigned long bist)
print_info("ht reset -\r\n");
soft_reset();
}
-
#if 0
print_pci_devices();
#endif
enable_smbus();
#if 0
- dump_spd_registers(&cpu[0]);
+ dump_spd_registers(sizeof(cpu)/sizeof(cpu[0]), cpu);
#endif
memreset_setup();
@@ -205,6 +238,8 @@ static void main(unsigned long bist)
#if 0
dump_pci_devices();
+#endif
+#if 0
dump_pci_device(PCI_DEV(0, 0x18, 2));
#endif
diff --git a/src/mainboard/arima/hdama/debug.c b/src/mainboard/arima/hdama/debug.c
new file mode 100644
index 0000000000..55c62649c8
--- /dev/null
+++ b/src/mainboard/arima/hdama/debug.c
@@ -0,0 +1,143 @@
+
+static void print_debug_pci_dev(unsigned dev)
+{
+ print_debug("PCI: ");
+ print_debug_hex8((dev >> 16) & 0xff);
+ print_debug_char(':');
+ print_debug_hex8((dev >> 11) & 0x1f);
+ print_debug_char('.');
+ print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+ device_t dev;
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ print_debug_pci_dev(dev);
+ print_debug("\r\n");
+ }
+}
+
+static void dump_pci_device(unsigned dev)
+{
+ int i;
+ print_debug_pci_dev(dev);
+ print_debug("\r\n");
+
+ for(i = 0; i <= 255; i++) {
+ unsigned char val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = pci_read_config8(dev, i);
+ print_debug_char(' ');
+ print_debug_hex8(val);
+ if ((i & 0x0f) == 0x0f) {
+ print_debug("\r\n");
+ }
+ }
+}
+
+static void dump_pci_devices(void)
+{
+ device_t dev;
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ dump_pci_device(dev);
+ }
+}
+
+static void dump_spd_registers(int controllers, const struct mem_controller *ctrl)
+{
+ int n;
+ for(n = 0; n < controllers; n++) {
+ int i;
+ print_debug("\r\n");
+ activate_spd_rom(&ctrl[n]);
+ for(i = 0; i < 4; i++) {
+ unsigned device;
+ device = ctrl[n].channel0[i];
+ if (device) {
+ int j;
+ print_debug("dimm: ");
+ print_debug_hex8(n);
+ print_debug_char('.');
+ print_debug_hex8(i);
+ print_debug(".0: ");
+ print_debug_hex8(device);
+ for(j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(j);
+ print_debug(": ");
+ }
+ status = spd_read_byte(device, j);
+ if (status < 0) {
+ print_debug("bad device\r\n");
+ break;
+ }
+#if 0
+ byte = status & 0xff;
+ print_debug_hex8(byte);
+#else
+ print_debug_hex8(status & 0xff);
+#endif
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+ }
+ device = ctrl[n].channel1[i];
+ if (device) {
+ int j;
+ print_debug("dimm: ");
+ print_debug_hex8(n);
+ print_debug_char('.');
+ print_debug_hex8(i);
+ print_debug(".1: ");
+ print_debug_hex8(device);
+ for(j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(j);
+ print_debug(": ");
+ }
+ status = spd_read_byte(device, j);
+ if (status < 0) {
+ print_debug("bad device\r\n");
+ break;
+ }
+#if 0
+ byte = status & 0xff;
+ print_debug_hex8(byte);
+#else
+ print_debug_hex8(status & 0xff);
+#endif
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+ }
+ }
+ }
+}
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 9287b7333e..ef32251e7d 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -4,6 +4,40 @@
#include <string.h>
#include <stdint.h>
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+ device_t dev;
+ unsigned reg;
+
+ dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+ if (!dev) {
+ return 0;
+ }
+ for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+ uint32_t config_map;
+ unsigned dst_node;
+ unsigned dst_link;
+ unsigned bus_base;
+ config_map = pci_read_config32(dev, reg);
+ if ((config_map & 3) != 3) {
+ continue;
+ }
+ dst_node = (config_map >> 4) & 7;
+ dst_link = (config_map >> 8) & 3;
+ bus_base = (config_map >> 16) & 0xff;
+#if 0
+ printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+ dst_node, dst_link, bus_base,
+ reg, config_map);
+#endif
+ if ((dst_node == node) && (dst_link == link))
+ {
+ return bus_base;
+ }
+ }
+ return 0;
+}
+
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
@@ -12,6 +46,7 @@ void *smp_write_config_table(void *v)
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
+ unsigned char bus_chain_0;
unsigned char bus_8131_1;
unsigned char bus_8131_2;
unsigned char bus_8111_1;
@@ -38,8 +73,15 @@ void *smp_write_config_table(void *v)
{
device_t dev;
+ /* HT chain 0 */
+ bus_chain_0 = node_link_to_bus(0, 0);
+ if (bus_chain_0 == 0) {
+ printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+ bus_chain_0 = 1;
+ }
+
/* 8111 */
- dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
+ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
@@ -52,7 +94,7 @@ void *smp_write_config_table(void *v)
bus_isa = 5;
}
/* 8131-1 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
+ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
@@ -63,7 +105,7 @@ void *smp_write_config_table(void *v)
bus_8131_1 = 2;
}
/* 8131-2 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
+ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
@@ -87,7 +129,7 @@ void *smp_write_config_table(void *v)
device_t dev;
struct resource *res;
/* 8131 apic 3 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
+ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
@@ -95,7 +137,7 @@ void *smp_write_config_table(void *v)
}
}
/* 8131 apic 4 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
+ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
diff --git a/src/mainboard/arima/hdama/reset.c b/src/mainboard/arima/hdama/reset.c
new file mode 100644
index 0000000000..3db3956ec6
--- /dev/null
+++ b/src/mainboard/arima/hdama/reset.c
@@ -0,0 +1,6 @@
+#include "../../../southbridge/amd/amd8111/amd8111_reset.c"
+
+void hard_reset(void)
+{
+ amd8111_hard_reset(0, 0);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-14 05:42:47 +0000