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-rw-r--r--src/mainboard/amd/bilby/mainboard.c53
-rw-r--r--src/mainboard/amd/birman/mainboard.c53
-rw-r--r--src/mainboard/amd/chausie/mainboard.c53
-rw-r--r--src/mainboard/amd/gardenia/mainboard.c58
-rw-r--r--src/mainboard/amd/majolica/mainboard.c53
-rw-r--r--src/mainboard/amd/mandolin/mainboard.c53
-rw-r--r--src/mainboard/amd/pademelon/mainboard.c43
7 files changed, 21 insertions, 345 deletions
diff --git a/src/mainboard/amd/bilby/mainboard.c b/src/mainboard/amd/bilby/mainboard.c
index ca856841d4..a751126ef7 100644
--- a/src/mainboard/amd/bilby/mainboard.c
+++ b/src/mainboard/amd/bilby/mainboard.c
@@ -9,7 +9,6 @@
#include <soc/southbridge.h>
#include <soc/pci_devs.h>
#include <soc/platform_descriptors.h>
-#include <string.h>
#include <types.h>
#include <commonlib/helpers.h>
#include <soc/amd/picasso/chip.h>
@@ -20,17 +19,8 @@
/* TODO: recheck IRQ tables */
-/*
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
-
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_A, 8, 16 },
{ PIRQ_B, 10, 17 },
@@ -56,41 +46,12 @@ static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_MISC2, 0x00, 0x00 },
};
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
-static void init_tables(void)
-{
- const struct fch_irq_routing *mb_irq_map;
- size_t mb_fch_irq_mapping_table_size;
- size_t i;
-
- mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
- memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
- memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
- for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
- if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
- printk(BIOS_WARNING,
- "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
- mb_irq_map[i].intr_index, i);
- continue;
- }
- fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
- fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
- }
-}
-
-static void pirq_setup(void)
-{
- intr_data_ptr = fch_apic_routing;
- picr_data_ptr = fch_pic_routing;
-}
-
static void program_display_sel_gpios(void)
{
int idx, port_type;
@@ -125,14 +86,6 @@ static void mainboard_init(void *chip_info)
mainboard_program_emmc_gpios();
}
-static void mainboard_enable(struct device *dev)
-{
- init_tables();
- /* Initialize the PIRQ data structures for consumption */
- pirq_setup();
-}
-
struct chip_operations mainboard_ops = {
.init = mainboard_init,
- .enable_dev = mainboard_enable,
};
diff --git a/src/mainboard/amd/birman/mainboard.c b/src/mainboard/amd/birman/mainboard.c
index 28c289de9e..6a7343f23a 100644
--- a/src/mainboard/amd/birman/mainboard.c
+++ b/src/mainboard/amd/birman/mainboard.c
@@ -2,25 +2,15 @@
#include <amdblocks/amd_pci_util.h>
#include <commonlib/helpers.h>
-#include <console/console.h>
#include <device/device.h>
#include <soc/acpi.h>
-#include <string.h>
#include <types.h>
#include "gpio.h"
/* TODO: Update for birman */
-/*
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
/*
* This controls the device -> IRQ routing.
@@ -61,54 +51,17 @@ static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_HPET_H, 0x00, 0x00 },
};
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
-static void init_tables(void)
-{
- const struct fch_irq_routing *mb_irq_map;
- size_t mb_fch_irq_mapping_table_size;
- size_t i;
-
- mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
- memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
- memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
- for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
- if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
- printk(BIOS_WARNING,
- "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
- mb_irq_map[i].intr_index, i);
- continue;
- }
- fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
- fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
- }
-}
-
-static void pirq_setup(void)
-{
- intr_data_ptr = fch_apic_routing;
- picr_data_ptr = fch_pic_routing;
-}
-
static void mainboard_init(void *chip_info)
{
mainboard_program_gpios();
}
-static void mainboard_enable(struct device *dev)
-{
- init_tables();
- /* Initialize the PIRQ data structures for consumption */
- pirq_setup();
-}
-
struct chip_operations mainboard_ops = {
.init = mainboard_init,
- .enable_dev = mainboard_enable,
};
diff --git a/src/mainboard/amd/chausie/mainboard.c b/src/mainboard/amd/chausie/mainboard.c
index 9515f2408e..17c9d7816b 100644
--- a/src/mainboard/amd/chausie/mainboard.c
+++ b/src/mainboard/amd/chausie/mainboard.c
@@ -2,23 +2,13 @@
#include <amdblocks/amd_pci_util.h>
#include <commonlib/helpers.h>
-#include <console/console.h>
#include <device/device.h>
#include <soc/acpi.h>
-#include <string.h>
#include <types.h>
#include "gpio.h"
-/*
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
/*
* This controls the device -> IRQ routing.
@@ -59,54 +49,17 @@ static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_HPET_H, 0x00, 0x00 },
};
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
-static void init_tables(void)
-{
- const struct fch_irq_routing *mb_irq_map;
- size_t mb_fch_irq_mapping_table_size;
- size_t i;
-
- mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
- memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
- memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
- for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
- if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
- printk(BIOS_WARNING,
- "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
- mb_irq_map[i].intr_index, i);
- continue;
- }
- fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
- fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
- }
-}
-
-static void pirq_setup(void)
-{
- intr_data_ptr = fch_apic_routing;
- picr_data_ptr = fch_pic_routing;
-}
-
static void mainboard_init(void *chip_info)
{
mainboard_program_gpios();
}
-static void mainboard_enable(struct device *dev)
-{
- init_tables();
- /* Initialize the PIRQ data structures for consumption */
- pirq_setup();
-}
-
struct chip_operations mainboard_ops = {
.init = mainboard_init,
- .enable_dev = mainboard_enable,
};
diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c
index 0bbb208500..ad95617512 100644
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -3,24 +3,13 @@
#include <device/device.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/amd_pci_util.h>
-#include <console/console.h>
#include <soc/gpio.h>
#include <soc/southbridge.h>
-#include <string.h>
#include "gpio.h"
-/*
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
-
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_A, 3, 16 },
{ PIRQ_B, 4, 17 },
@@ -53,42 +42,12 @@ static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_MISC2, 0x00, 0x00 },
};
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
-static void init_tables(void)
-{
- const struct fch_irq_routing *mb_irq_map;
- size_t mb_fch_irq_mapping_table_size;
- size_t i;
-
- mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
- memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
- memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
- for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
- if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
- printk(BIOS_WARNING,
- "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
- mb_irq_map[i].intr_index, i);
- continue;
- }
- fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
- fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
- }
-}
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
- intr_data_ptr = fch_apic_routing;
- picr_data_ptr = fch_pic_routing;
-}
-
static void mainboard_init(void *chip_info)
{
size_t num_gpios;
@@ -97,17 +56,6 @@ static void mainboard_init(void *chip_info)
gpio_configure_pads(gpios, num_gpios);
}
-/*************************************************
- * enable the dedicated function in gardenia board.
- *************************************************/
-static void mainboard_enable(struct device *dev)
-{
- init_tables();
- /* Initialize the PIRQ data structures for consumption */
- pirq_setup();
-}
-
struct chip_operations mainboard_ops = {
.init = mainboard_init,
- .enable_dev = mainboard_enable,
};
diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c
index a5e2935f4a..9dbd4e42ee 100644
--- a/src/mainboard/amd/majolica/mainboard.c
+++ b/src/mainboard/amd/majolica/mainboard.c
@@ -2,22 +2,12 @@
#include <amdblocks/amd_pci_util.h>
#include <commonlib/helpers.h>
-#include <console/console.h>
#include <device/device.h>
#include <soc/acpi.h>
-#include <string.h>
#include <types.h>
-/*
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
/*
* This controls the device -> IRQ routing.
@@ -59,53 +49,16 @@ static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_HPET_H, 0x00, 0x00 },
};
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
-static void init_tables(void)
-{
- const struct fch_irq_routing *mb_irq_map;
- size_t mb_fch_irq_mapping_table_size;
- size_t i;
-
- mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
- memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
- memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
- for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
- if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
- printk(BIOS_WARNING,
- "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
- mb_irq_map[i].intr_index, i);
- continue;
- }
- fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
- fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
- }
-}
-
-static void pirq_setup(void)
-{
- intr_data_ptr = fch_apic_routing;
- picr_data_ptr = fch_pic_routing;
-}
-
static void mainboard_init(void *chip_info)
{
}
-static void mainboard_enable(struct device *dev)
-{
- init_tables();
- /* Initialize the PIRQ data structures for consumption */
- pirq_setup();
-}
-
struct chip_operations mainboard_ops = {
.init = mainboard_init,
- .enable_dev = mainboard_enable,
};
diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c
index 397179a68a..6a275145eb 100644
--- a/src/mainboard/amd/mandolin/mainboard.c
+++ b/src/mainboard/amd/mandolin/mainboard.c
@@ -7,7 +7,6 @@
#include <soc/cpu.h>
#include <soc/southbridge.h>
#include <soc/pci_devs.h>
-#include <string.h>
#include <types.h>
#include <commonlib/helpers.h>
#include <soc/amd/picasso/chip.h>
@@ -15,17 +14,8 @@
/* TODO: recheck IRQ tables */
-/*
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
-
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_A, 8, 16 },
{ PIRQ_B, 10, 17 },
@@ -51,41 +41,12 @@ static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_MISC2, 0x00, 0x00 },
};
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
-static void init_tables(void)
-{
- const struct fch_irq_routing *mb_irq_map;
- size_t mb_fch_irq_mapping_table_size;
- size_t i;
-
- mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
- memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
- memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
- for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
- if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
- printk(BIOS_WARNING,
- "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
- mb_irq_map[i].intr_index, i);
- continue;
- }
- fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
- fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
- }
-}
-
-static void pirq_setup(void)
-{
- intr_data_ptr = fch_apic_routing;
- picr_data_ptr = fch_pic_routing;
-}
-
static void mainboard_init(void *chip_info)
{
struct soc_amd_picasso_config *cfg = config_of_soc();
@@ -102,14 +63,6 @@ static void mainboard_init(void *chip_info)
mainboard_program_emmc_gpios();
}
-static void mainboard_enable(struct device *dev)
-{
- init_tables();
- /* Initialize the PIRQ data structures for consumption */
- pirq_setup();
-}
-
struct chip_operations mainboard_ops = {
.init = mainboard_init,
- .enable_dev = mainboard_enable,
};
diff --git a/src/mainboard/amd/pademelon/mainboard.c b/src/mainboard/amd/pademelon/mainboard.c
index 9c558088c2..12f0443196 100644
--- a/src/mainboard/amd/pademelon/mainboard.c
+++ b/src/mainboard/amd/pademelon/mainboard.c
@@ -3,25 +3,14 @@
#include <device/device.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/amd_pci_util.h>
-#include <console/console.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
-#include <string.h>
#include "gpio.h"
-/*
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
-
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_A, 3, 16 },
{ PIRQ_B, 4, 17 },
@@ -54,35 +43,12 @@ static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_MISC2, 0x00, 0x00 },
};
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
-static void init_tables(void)
-{
- const struct fch_irq_routing *mb_irq_map;
- size_t mb_fch_irq_mapping_table_size;
- size_t i;
-
- mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
- memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
- memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
- for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
- if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
- printk(BIOS_WARNING,
- "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
- mb_irq_map[i].intr_index, i);
- continue;
- }
- fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
- fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
- }
-}
-
/*
* This table defines the index into the picr/intr_data tables for each
* device. Any enabled device and slot that uses hardware interrupts should
@@ -113,8 +79,6 @@ static void pirq_setup(void)
{
pirq_data_ptr = mainboard_pirq_data;
pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
- intr_data_ptr = fch_apic_routing;
- picr_data_ptr = fch_pic_routing;
}
static void mainboard_init(void *chip_info)
@@ -130,7 +94,6 @@ static void mainboard_init(void *chip_info)
*************************************************/
static void mainboard_enable(struct device *dev)
{
- init_tables();
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-20 17:51:59 +0000