diff options
Diffstat (limited to 'src/mainboard/amd')
22 files changed, 0 insertions, 1075 deletions
diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c deleted file mode 100644 index d97f2b0a6a..0000000000 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <FchPlatform.h> - -#include "imc.h" - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } -}; -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); - -/** - * AMD Olivehill Platform ALC272 Verb Table - */ -static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT - {0xff, 0xffffffff} -}; - -static const CODEC_TBL_LIST OlivehillCodecTableList[] = -{ - {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Olivehill Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperature via I2C, - * if other software switches the I2C switch by mistake or intention. - * We recommend using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control, the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. - * So we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommended */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - -void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) -{ -} - -void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) -{ - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]); - - /* Fan Control */ - oem_fan_control(FchParams_env); -} diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig deleted file mode 100644 index e69f3e62bf..0000000000 --- a/src/mainboard/amd/olivehill/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_AMD_OLIVEHILL - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_AMD_AGESA_FAMILY16_KB - select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB - select SOUTHBRIDGE_AMD_AGESA_YANGTZE - select DEFAULT_POST_ON_LPC - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA - -config MAINBOARD_DIR - default "amd/olivehill" - -config MAINBOARD_PART_NUMBER - default "DB-FT3" - -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - -config HUDSON_LEGACY_FREE - bool - default y - -endif # BOARD_AMD_OLIVEHILL diff --git a/src/mainboard/amd/olivehill/Kconfig.name b/src/mainboard/amd/olivehill/Kconfig.name deleted file mode 100644 index fd1a713aac..0000000000 --- a/src/mainboard/amd/olivehill/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_OLIVEHILL - bool "Olive Hill" diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc deleted file mode 100644 index 549801d78f..0000000000 --- a/src/mainboard/amd/olivehill/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += bootblock.c - -romstage-y += buildOpts.c -romstage-y += BiosCallOuts.c -romstage-y += OemCustomize.c - -ramstage-y += buildOpts.c -ramstage-y += BiosCallOuts.c -ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c deleted file mode 100644 index 18db54049e..0000000000 --- a/src/mainboard/amd/olivehill/OemCustomize.c +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> -#include <PlatformMemoryConfiguration.h> - -#include <northbridge/amd/agesa/state_machine.h> - -static const PCIe_PORT_DESCRIPTOR PortList[] = { - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x01, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x02, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x03, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x04, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x05, 0) - } -}; - -static const PCIe_DDI_DESCRIPTOR DdiList[] = { - /* DP0 to HDMI0/DP */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) - }, - /* DP1 to FCH */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) - }, - /* DP2 to HDMI1/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3) - }, -}; - -static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, - .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList -}; - -void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) -{ - FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = FALSE; -} - -void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) -{ - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; -} - -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERRIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { - #define SEED_A 0x12 - HW_RXEN_SEED( - ANY_SOCKET, CHANNEL_A, ALL_DIMMS, - SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, - SEED_A), - - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), - MOTHER_BOARD_LAYERS(LAYERS_4), - - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), - - PSO_END -}; - -void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) -{ - InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; -} - -void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; -} diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h deleted file mode 100644 index 130d8525ab..0000000000 --- a/src/mainboard/amd/olivehill/OptionsIds.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -#endif diff --git a/src/mainboard/amd/olivehill/acpi/gpe.asl b/src/mainboard/amd/olivehill/acpi/gpe.asl deleted file mode 100644 index 778c7f73be..0000000000 --- a/src/mainboard/amd/olivehill/acpi/gpe.asl +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope(\_GPE) { /* Start Scope GPE */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ - } - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } -} /* End Scope GPE */ diff --git a/src/mainboard/amd/olivehill/acpi/mainboard.asl b/src/mainboard/amd/olivehill/acpi/mainboard.asl deleted file mode 100644 index 9b18e722c7..0000000000 --- a/src/mainboard/amd/olivehill/acpi/mainboard.asl +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - -/* AcpiGpe0Blk */ -OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, -} diff --git a/src/mainboard/amd/olivehill/acpi/routing.asl b/src/mainboard/amd/olivehill/acpi/routing.asl deleted file mode 100644 index 9bce4b2163..0000000000 --- a/src/mainboard/amd/olivehill/acpi/routing.asl +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Routing is in System Bus scope */ -Name(PR0, Package(){ - /* NB devices */ - /* Bus 0, Dev 0 - F16 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ - Package(){0x0001FFFF, 0, INTB, 0 }, - Package(){0x0001FFFF, 1, INTC, 0 }, - - /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - - /* FCH devices */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, INTC, 0 }, - Package(){0x0012FFFF, 1, INTB, 0 }, - - Package(){0x0013FFFF, 0, INTC, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - - Package(){0x0016FFFF, 0, INTC, 0 }, - Package(){0x0016FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, INTC, 0 }, - Package(){0x0010FFFF, 1, INTB, 0 }, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, INTD, 0 }, - -}) - -Name(APR0, Package(){ - /* NB devices in APIC mode */ - /* Bus 0, Dev 0 - F15 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package(){0x0001FFFF, 0, 0, 44 }, - Package(){0x0001FFFF, 1, 0, 45 }, - - /* Bus 0, Dev 2 - PCIe Bridges */ - Package(){0x0002FFFF, 0, 0, 24 }, - Package(){0x0002FFFF, 1, 0, 25 }, - Package(){0x0002FFFF, 2, 0, 26 }, - Package(){0x0002FFFF, 3, 0, 27 }, - - /* SB devices in APIC mode */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - - /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ - /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ - Package(){0x0012FFFF, 0, 0, 18 }, - Package(){0x0012FFFF, 1, 0, 17 }, - - Package(){0x0013FFFF, 0, 0, 18 }, - Package(){0x0013FFFF, 1, 0, 17 }, - - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, - - /* Bus 0, Dev 17 - SATA controller */ - Package(){0x0011FFFF, 0, 0, 19 }, - -}) - -Name(PS2, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS2, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, -}) - -/* GFX */ -Name(PS4, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 24 }, - Package(){0x0000FFFF, 1, 0, 25 }, - Package(){0x0000FFFF, 2, 0, 26 }, - Package(){0x0000FFFF, 3, 0, 27 }, -}) - -/* GPP 0 */ -Name(PS5, Package(){ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, -}) -Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 28 }, - Package(){0x0000FFFF, 1, 0, 29 }, - Package(){0x0000FFFF, 2, 0, 30 }, - Package(){0x0000FFFF, 3, 0, 31 }, -}) - -/* GPP 1 */ -Name(PS6, Package(){ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, -}) -Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 32 }, - Package(){0x0000FFFF, 1, 0, 33 }, - Package(){0x0000FFFF, 2, 0, 34 }, - Package(){0x0000FFFF, 3, 0, 35 }, -}) - -/* GPP 2 */ -Name(PS7, Package(){ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, -}) -Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 36 }, - Package(){0x0000FFFF, 1, 0, 37 }, - Package(){0x0000FFFF, 2, 0, 38 }, - Package(){0x0000FFFF, 3, 0, 39 }, -}) - -/* GPP 3 */ -Name(PS8, Package(){ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, -}) -Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 40 }, - Package(){0x0000FFFF, 1, 0, 41 }, - Package(){0x0000FFFF, 2, 0, 42 }, - Package(){0x0000FFFF, 3, 0, 43 }, -}) diff --git a/src/mainboard/amd/olivehill/acpi/sata.asl b/src/mainboard/amd/olivehill/acpi/sata.asl deleted file mode 100644 index 659a076e19..0000000000 --- a/src/mainboard/amd/olivehill/acpi/sata.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* No SATA functionality */ diff --git a/src/mainboard/amd/olivehill/acpi/sleep.asl b/src/mainboard/amd/olivehill/acpi/sleep.asl deleted file mode 100644 index fc26c306d9..0000000000 --- a/src/mainboard/amd/olivehill/acpi/sleep.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Wake status package */ -Name(WKST,Package(){Zero, Zero}) - -/* -* \_PTS - Prepare to Sleep method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2, etc -* -* Exit: -* -none- -* -* The _PTS control method is executed at the beginning of the sleep process -* for S1-S5. The sleeping value is passed to the _PTS control method. This -* control method may be executed a relatively long time before entering the -* sleep state and the OS may abort the operation without notification to -* the ACPI driver. This method cannot modify the configuration or power -* state of any device in the system. -*/ - -External(\_SB.APTS, MethodObj) -External(\_SB.AWAK, MethodObj) - -Method(_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Clear wake status structure. */ - WKST [0] = 0 - WKST [1] = 0 - UPWS = 7 - \_SB.APTS(Arg0) -} /* End Method(\_PTS) */ - -/* -* \_WAK System Wake method -* -* Entry: -* Arg0=The value of the sleeping state S1=1, S2=2 -* -* Exit: -* Return package of 2 DWords -* Dword 1 - Status -* 0x00000000 wake succeeded -* 0x00000001 Wake was signaled but failed due to lack of power -* 0x00000002 Wake was signaled but failed due to thermal condition -* Dword 2 - Power Supply state -* if non-zero the effective S-state the power supply entered -*/ -Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - USBS = 1 - - \_SB.AWAK(Arg0) - - Return(WKST) -} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/olivehill/acpi/superio.asl b/src/mainboard/amd/olivehill/acpi/superio.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/amd/olivehill/acpi/superio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/amd/olivehill/acpi/thermal.asl b/src/mainboard/amd/olivehill/acpi/thermal.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/mainboard/amd/olivehill/acpi/thermal.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/amd/olivehill/acpi/usb_oc.asl b/src/mainboard/amd/olivehill/acpi/usb_oc.asl deleted file mode 100644 index a5846fe848..0000000000 --- a/src/mainboard/amd/olivehill/acpi/usb_oc.asl +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) diff --git a/src/mainboard/amd/olivehill/board_info.txt b/src/mainboard/amd/olivehill/board_info.txt deleted file mode 100644 index b351b8e696..0000000000 --- a/src/mainboard/amd/olivehill/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/amd/olivehill/bootblock.c b/src/mainboard/amd/olivehill/bootblock.c deleted file mode 100644 index 319914fe7b..0000000000 --- a/src/mainboard/amd/olivehill/bootblock.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <arch/io.h> -#include <bootblock_common.h> - -void bootblock_mainboard_early_init(void) -{ - int i; - - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - pm_write8(0xea, 0x1); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - for (i = 0; i < 200000; i++) - inb(0xcd6); -} diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c deleted file mode 100644 index 7a1f3590de..0000000000 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <AGESA.h> - -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE - -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE - -/* Build configuration values here. */ -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_SYNC_FLOOD TRUE - -#define BLDCFG_IOMMU_SUPPORT FALSE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE - -/* Include the files that instantiate the configuration definitions. */ -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -#include <PlatformInstall.h> diff --git a/src/mainboard/amd/olivehill/cmos.layout b/src/mainboard/amd/olivehill/cmos.layout deleted file mode 100644 index a11e1dd0e6..0000000000 --- a/src/mainboard/amd/olivehill/cmos.layout +++ /dev/null @@ -1,35 +0,0 @@ -#***************************************************************************** -# SPDX-License-Identifier: GPL-2.0-only - -#***************************************************************************** - -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/amd/olivehill/devicetree.cb b/src/mainboard/amd/olivehill/devicetree.cb deleted file mode 100644 index 05dc7234b4..0000000000 --- a/src/mainboard/amd/olivehill/devicetree.cb +++ /dev/null @@ -1,52 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip northbridge/amd/agesa/family16kb/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family16kb - device lapic 0 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - end #chip northbridge/amd/agesa/family16kb - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/agesa/hudson - - chip northbridge/amd/agesa/family16kb - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end - - end #domain -end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl deleted file mode 100644 index c86cf27f67..0000000000 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* DefinitionBlock Statement */ -#include <acpi/acpi.h> -DefinitionBlock ( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - #include <acpi/dsdt_top.asl> - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_SB) */ - #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" - - /* Define the Thermal zones and methods for the platform */ - #include "acpi/thermal.asl" -} -/* End of ASL file */ diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c deleted file mode 100644 index e5d576a349..0000000000 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <commonlib/bsd/helpers.h> -#include <device/pci_def.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr = ALIGN_UP(addr, 16); - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *)(addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* PCI bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) - pirq->checksum = sum; - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; -} diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c deleted file mode 100644 index 3ebc0c1cd5..0000000000 --- a/src/mainboard/amd/olivehill/mainboard.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <southbridge/amd/common/amd_pci_util.h> - -static const u8 mainboard_picr_data[0x54] = { - 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x03, 0x04, 0x05, 0x07 -}; -static const u8 mainboard_intr_data[0x54] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x10, 0x11, 0x12, 0x13 -}; - -/* PIRQ Setup */ -static void pirq_setup(void) -{ - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; -} - -/********************************************** - * enable the dedicated function in mainboard. - **********************************************/ -static void mainboard_enable(struct device *dev) -{ - pirq_setup(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; |