diff options
Diffstat (limited to 'src/mainboard/amd/solo')
| -rw-r--r-- | src/mainboard/amd/solo/Config.lb | 221 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/Options.lb | 209 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/acpi_tables.c | 101 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/auto.c | 152 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/chip.h | 5 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/cmos.layout | 98 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/failover.c | 68 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/irq_tables.c | 59 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/mainboard.c | 7 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/mptable.c | 241 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/reset.c | 6 |
11 files changed, 0 insertions, 1167 deletions
diff --git a/src/mainboard/amd/solo/Config.lb b/src/mainboard/amd/solo/Config.lb deleted file mode 100644 index f7efc861ad..0000000000 --- a/src/mainboard/amd/solo/Config.lb +++ /dev/null @@ -1,221 +0,0 @@ -## -## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The linuxBIOS bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of linuxBIOS will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up linuxBIOS, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_ACPI_TABLES object acpi_tables.o end -#object reset.o - -## -## Romcc output -## -makerule ./failover.E - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" - action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ./romcc" - action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit linuxBIOS entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where linuxBIOS is entered) -## -if USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of linuxBIOS startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu/enable_fpu.inc -mainboardinit cpu/x86/mmx/enable_mmx.inc -mainboardinit cpu/x86/sse/enable_sse.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse/disable_sse.inc -mainboardinit cpu/x86/mmx/disable_mmx.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -# sample config for arima/hdama -chip northbridge/amd/amdk8/root_complex - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8151 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 1.0 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 on end - device pci 1.0 off end - end - device pci 1.0 on - chip superio/nsc/pc87360 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/generic/generic - #phillips pca9545 smbus mux - device i2c 70 on - # analog_devices adm1026 - chip drivers/generic/generic - device i2c 2c on end - end - end - device i2c 70 on end - device i2c 70 on end - device i2c 70 on end - end - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end - device pci 1.5 off end - device pci 1.6 on end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.0 on end # LDT1 - device pci 18.0 on end # LDT2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end - device apic_cluster 0 on - chip cpu/amd/socket_754 - device apic 0 on end - end - end -end - diff --git a/src/mainboard/amd/solo/Options.lb b/src/mainboard/amd/solo/Options.lb deleted file mode 100644 index beef9278c2..0000000000 --- a/src/mainboard/amd/solo/Options.lb +++ /dev/null @@ -1,209 +0,0 @@ -uses HAVE_MP_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses FALLBACK_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses LINUXBIOS_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CROSS_COMPILE -uses CC -uses HOSTCC -uses OBJCOPY - -uses CONFIG_USE_INIT - - -### -### Build options -### - -## -## ROM_SIZE is the size of boot ROM that this board will use. -## -default ROM_SIZE=524288 - -## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default FALLBACK_SIZE=0x40000 - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from linuxBIOS -## -default HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default HAVE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=1 - -## -## Move the default LinuxBIOS cmos range off of AMD RTC registers -## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=1 -default CONFIG_MAX_PHYSICAL_CPUS=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default MAINBOARD_PART_NUMBER="SOLO" -default MAINBOARD_VENDOR="AMD" - -### -### LinuxBIOS layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -default ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE - -## -## LinuxBIOS C code runs at this location in RAM -## -default _RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 - -# Select the serial console base port -default TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 - -## -### Select the linuxBIOS loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/amd/solo/acpi_tables.c b/src/mainboard/amd/solo/acpi_tables.c deleted file mode 100644 index 9c2aeadd2d..0000000000 --- a/src/mainboard/amd/solo/acpi_tables.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * LinuxBIOS ACPI support for AMD Solo - * written by Stefan Reinauer <stepan@openbios.org> - * (C) 2005 Stefan Reinauer - */ - -#include <console/console.h> -#include <string.h> -#include <arch/acpi.h> -#include <device/pci.h> - - -unsigned long acpi_dump_apics(unsigned long current) -{ -#define IO_APIC_ADDR 0xfec00000UL - /* create all subtables for 1p */ - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, - IO_APIC_ADDR); - current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) - current, 0, 0, 2, 1 /* active high */); - current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xf /* active low, level triggered */); - current += acpi_create_madt_lapic_nmi( (acpi_madt_lapic_nmi_t *) - current, 0, 5, 1); - return current; -} - -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *dsdt; - - /* Align ACPI tables to 16byte */ - start = ( start + 0x0f ) & -0x10; - current = start; - - printk_info("ACPI: Writing ACPI tables at %lx...\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt); - acpi_write_rsdt(rsdt); - - /* - * We explicitly add these tables later on: - */ - printk_debug("ACPI: * HPET\n"); - - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); - acpi_add_table(rsdt,hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - printk_debug("ACPI: * MADT\n"); - - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current+=madt->header.length; - acpi_add_table(rsdt,madt); - -#ifdef HAVE_ACPI_FADT - printk_debug("ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - - dsdt = (acpi_header_t *)current; - current += ((acpi_header_t *)AmlCode)->length; - memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length); - dsdt->checksum = 0; // don't trust intel iasl compiler to get this right - dsdt->checksum = acpi_checksum(dsdt,dsdt->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); - printk_debug("ACPI: * FADT\n"); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt,facs,dsdt); - acpi_add_table(rsdt,fadt); -#endif - - printk_info("ACPI: done.\n"); - return current; -} - diff --git a/src/mainboard/amd/solo/auto.c b/src/mainboard/amd/solo/auto.c deleted file mode 100644 index 34a79cb514..0000000000 --- a/src/mainboard/amd/solo/auto.c +++ /dev/null @@ -1,152 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include <arch/cpu.h> -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "ram/ramtest.c" -#include "southbridge/amd/amd8111/amd8111_early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" -#include <cpu/amd/model_fxx_rev.h> -#include "superio/nsc/pc87360/pc87360_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" -#include "cpu/x86/bist.h" - -#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) - -static void hard_reset(void) -{ - set_bios_reset(); - - /* enable cf9 */ - pci_write_config8(PCI_DEV(0, 0x05, 3), 0x41, 0xf1); - /* reset */ - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - set_bios_reset(); - pci_write_config8(PCI_DEV(0, 0x05, 0), 0x47, 1); -} - -static void memreset_setup(void) -{ - if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | - (0 << 0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | - (0 << 0), SMBUS_IO_BASE + 0xc0 + 29); - } else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | - (1 << 0), SMBUS_IO_BASE + 0xc0 + 29); - } -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - if (is_cpu_pre_c0()) { - udelay(800); - /* Set memreset_high */ - outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | - (1 << 0), SMBUS_IO_BASE + 0xc0 + 28); - udelay(90); - } -} - -static unsigned int generate_row(uint8_t node, uint8_t row, - uint8_t maxnodes) -{ - /* since the AMD Solo is a UP only machine, we can - * always return the default row entry value - */ - return 0x00010101; /* default row entry */ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/amd/amdk8/raminit.c" -#include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "cpu/amd/dualcore/dualcore.c" -#include "sdram/generic_sdram.c" -#include "northbridge/amd/amdk8/resourcemap.c" - -static void main(unsigned long bist) -{ - static const struct mem_controller cpu[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = {(0xa << 3) | 0, (0xa << 3) | 1, 0, 0}, - .channel1 = {0, 0, 0, 0}, - } - }; - - int needs_reset; - unsigned nodeid; - - if (bist == 0) { - k8_init_and_stop_secondaries(); - } - - /* Setup the console */ - pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - setup_default_resource_map(); - needs_reset = setup_coherent_ht_domain(); - needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); - if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); - } - -#if 0 - print_pci_devices(); -#endif - enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif - - memreset_setup(); - sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu); - -#if 0 - dump_pci_devices(); - dump_pci_device(PCI_DEV(0, 0x18, 2)); - - /* Check the first 1M */ - ram_check(0x00000000, 0x000100000); -#endif -} diff --git a/src/mainboard/amd/solo/chip.h b/src/mainboard/amd/solo/chip.h deleted file mode 100644 index 941c656e2e..0000000000 --- a/src/mainboard/amd/solo/chip.h +++ /dev/null @@ -1,5 +0,0 @@ -extern struct chip_operations mainboard_amd_solo_ops; - -struct mainboard_amd_solo_config { - int nothing; -}; diff --git a/src/mainboard/amd/solo/cmos.layout b/src/mainboard/amd/solo/cmos.layout deleted file mode 100644 index 5eb88b9a5a..0000000000 --- a/src/mainboard/amd/solo/cmos.layout +++ /dev/null @@ -1,98 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 dual_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 - - diff --git a/src/mainboard/amd/solo/failover.c b/src/mainboard/amd/solo/failover.c deleted file mode 100644 index 1738e908d9..0000000000 --- a/src/mainboard/amd/solo/failover.c +++ /dev/null @@ -1,68 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include "pc80/mc146818rtc_early.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" -#include "northbridge/amd/amdk8/early_ht.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "northbridge/amd/amdk8/reset_test.c" - -static unsigned long main(unsigned long bist) -{ - unsigned nodeid; - - /* Make cerain my local apic is useable */ - enable_lapic(); - - nodeid = lapicid() & 0xf; - - /* Is this a cpu only reset? */ - if (early_mtrr_init_detected()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - /* Is this a secondary cpu? */ - if (!boot_cpu()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the 8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} diff --git a/src/mainboard/amd/solo/irq_tables.c b/src/mainboard/amd/solo/irq_tables.c deleted file mode 100644 index 783d8bd7b8..0000000000 --- a/src/mainboard/amd/solo/irq_tables.c +++ /dev/null @@ -1,59 +0,0 @@ -#include <arch/pirq_routing.h> -#include <device/pci.h> - -#define IRQ_ROUTER_BUS 1 -#define IRQ_ROUTER_DEVFN PCI_DEVFN(5,0) -#define IRQ_ROUTER_VENDOR 0x1022 -#define IRQ_ROUTER_DEVICE 0x7468 -#define IRQS_EXCLUSIVE 0x0c20 -#define IRQS_AVAILABLE 0xdeb8 - - -#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \ - { bus, (dev<<3)|fn, {{ linka, IRQS_AVAILABLE}, { linkb, IRQS_AVAILABLE}, \ - {linkc, IRQS_AVAILABLE}, {linkd, IRQS_AVAILABLE}}, slot, 0} - -/* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu - */ - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT - * devices on the bus */ - IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ - IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ - IRQS_EXCLUSIVE, /* IRQs devoted exclusively to PCI usage */ - IRQ_ROUTER_VENDOR, /* Vendor */ - IRQ_ROUTER_DEVICE, /* Device */ - 0x00, /* Crap (miniport) */ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ - 0x00, /* u8 checksum , mod 256 checksum must give - * zero, will be corrected later - */ - { - - /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */ - - /* PCI SLOT 1-4 */ - IRQ_SLOT(1, 3, 4, 0, 1, 2, 3, 4), - IRQ_SLOT(2, 3, 5, 0, 2, 3, 4, 1), - IRQ_SLOT(3, 3, 6, 0, 3, 4, 1, 2), - IRQ_SLOT(4, 3, 7, 0, 4, 1, 2, 3), - - /* Builtin Devices */ - IRQ_SLOT(0, 3, 0, 0, 4, 4, 4, 4), /* USB */ - IRQ_SLOT(0, 1, 5, 1, 1, 2, 3, 4), /* IDE */ - IRQ_SLOT(0, 1, 2, 0, 1, 2, 3, 4), /* AGP Bridge */ - - /* Let Linux know about bus 1 */ - IRQ_SLOT(0, 1, 5, 0, 0, 0, 0, 0), - - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr); -} diff --git a/src/mainboard/amd/solo/mainboard.c b/src/mainboard/amd/solo/mainboard.c deleted file mode 100644 index 4c482402c1..0000000000 --- a/src/mainboard/amd/solo/mainboard.c +++ /dev/null @@ -1,7 +0,0 @@ -#include <device/device.h> -#include "chip.h" - -struct chip_operations mainboard_amd_solo_ops = { - CHIP_NAME("AMD Solo7 Mainboard") -}; - diff --git a/src/mainboard/amd/solo/mptable.c b/src/mainboard/amd/solo/mptable.c deleted file mode 100644 index a21a49489b..0000000000 --- a/src/mainboard/amd/solo/mptable.c +++ /dev/null @@ -1,241 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -void *smp_write_config_table(void *v) -{ - static const char sig[4] = "PCMP"; - static const char oem[8] = "AMD "; - static const char productid[12] = "SOLO7 "; - struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; - unsigned char bus_8151_1; - unsigned char bus_8111_1; - - mc = (void *) (((char *) v) + SMP_FLOATING_TABLE_LEN); - memset(mc, 0, sizeof(*mc)); - - memcpy(mc->mpc_signature, sig, sizeof(sig)); - mc->mpc_length = sizeof(*mc); /* initially just the header */ - mc->mpc_spec = 0x04; - mc->mpc_checksum = 0; /* not yet computed */ - memcpy(mc->mpc_oem, oem, sizeof(oem)); - memcpy(mc->mpc_productid, productid, sizeof(productid)); - mc->mpc_oemptr = 0; - mc->mpc_oemsize = 0; - mc->mpc_entry_count = 0; /* No entries yet... */ - mc->mpc_lapic = LAPIC_ADDR; - mc->mpe_length = 0; - mc->mpe_checksum = 0; - mc->reserved = 0; - - smp_write_processors(mc); - - { - device_t dev; - - printk_info("creating mp table...\n"); - - /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x04, 0)); - if (dev) { - bus_8111_1 = - pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = - pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - printk_debug(" mptable: 8111 PCI bus %d\n", - bus_8111_1); - printk_debug(" mptable: 8111 ISA bus %d\n", - bus_isa); - } else { - printk_debug - ("ERROR - could not find 8111 at PCI 1:04.0, using defaults\n"); - - bus_8111_1 = 3; - bus_isa = 4; - } - /* 8151-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01, 0)); - if (dev) { - bus_8151_1 = - pci_read_config8(dev, PCI_SECONDARY_BUS); - printk_debug(" mptable: 8151 PCI bus %d\n", - bus_8151_1); - } else { - printk_debug - ("ERROR - could not find 8151 at PCI 1:01.0, using defaults\n"); - - bus_8151_1 = 2; - } - } - - /* define bus and isa numbers */ - for (bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); - - /* IOAPIC handling */ - - smp_write_ioapic(mc, 2, 0x11, 0xfec00000); - - /* ISA backward compatibility interrupts */ - smp_write_intsrc(mc, mp_ExtINT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x00, 0x02, 0x00); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x01, 0x02, 0x01); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x00, 0x02, 0x02); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x03, 0x02, 0x03); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x04, 0x02, 0x04); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x05, 0x02, 0x05); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x06, 0x02, 0x06); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x07, 0x02, 0x07); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x08, 0x02, 0x08); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x09, 0x02, 0x09); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0a, 0x02, 0x0a); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0b, 0x02, 0x0b); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0c, 0x02, 0x0c); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0d, 0x02, 0x0d); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0e, 0x02, 0x0e); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x0f, 0x02, 0x0f); - - /* Standard local interrupt assignments */ - smp_write_lintsrc(mc, mp_ExtINT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x00, MP_APIC_ALL, 0x00); - smp_write_lintsrc(mc, mp_NMI, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_isa, 0x00, MP_APIC_ALL, 0x01); - - - /* AGP Slot */ - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8151_1, (0 << 2) | 0, 0x02, 0x10); - - /* PCI Slot 1 */ -#warning "FIXME get the irqs right, it's just hacked to work for now" - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4 << 2) | 0, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4 << 2) | 1, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4 << 2) | 2, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (4 << 2) | 3, 0x02, 0x13); - - - /* PCI Slot 2 */ -#warning "FIXME get the irqs right, it's just hacked to work for now" - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5 << 2) | 0, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5 << 2) | 1, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5 << 2) | 2, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (5 << 2) | 3, 0x02, 0x10); - - - /* PCI Slot 3 */ -#warning "FIXME get the irqs right, it's just hacked to work for now" - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (6 << 2) | 0, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (6 << 2) | 1, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (6 << 2) | 2, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (6 << 2) | 3, 0x02, 0x11); - - /* PCI Slot 4 */ -#warning "FIXME get the irqs right, it's just hacked to work for now" - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (7 << 2) | 0, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (7 << 2) | 1, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (7 << 2) | 2, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - bus_8111_1, (7 << 2) | 3, 0x02, 0x12); - - /* Local devices */ - - /* USB */ - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - bus_8111_1, (0 << 2) | 3, 0x02, 0x13); - /* Sound */ - smp_write_intsrc(mc, mp_INT, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, - 1, (5 << 2) | 1, 0x02, 0x11); - - - /* There is no extension information... */ - - /* Compute the checksums */ - mc->mpe_checksum = - smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); - - mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); - printk_debug("Wrote the mp table end at: %p - %p\n", - mc, smp_next_mpe_entry(mc)); - return smp_next_mpe_entry(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr); - return (unsigned long) smp_write_config_table(v); -} diff --git a/src/mainboard/amd/solo/reset.c b/src/mainboard/amd/solo/reset.c deleted file mode 100644 index 3db3956ec6..0000000000 --- a/src/mainboard/amd/solo/reset.c +++ /dev/null @@ -1,6 +0,0 @@ -#include "../../../southbridge/amd/amd8111/amd8111_reset.c" - -void hard_reset(void) -{ - amd8111_hard_reset(0, 0); -} |