diff options
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah_fam10/Config.lb')
-rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/Config.lb | 424 |
1 files changed, 424 insertions, 0 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb new file mode 100644 index 0000000000..35ab8aa36d --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb @@ -0,0 +1,424 @@ +# +# This file is part of the LinuxBIOS project. +# +# Copyright (C) 2007 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FAILOVER_IMAGE + default ROM_SECTION_SIZE = FAILOVER_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) +else + if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + default ROM_SECTION_OFFSET = 0 + end +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +# +if USE_FAILOVER_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) +else + if USE_FALLBACK_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) + else + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) + end +end + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + + +#needed by irq_tables and mptable and acpi_tables +object get_bus_conf.o + +if HAVE_MP_TABLE + object mptable.o +end + +if HAVE_PIRQ_TABLE + object irq_tables.o +end + +if HAVE_ACPI_TABLES + object acpi_tables.o + object fadt.o + makerule dsdt.c + depends "$(MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + action "mv dsdt_lb.hex dsdt.c" + end + object ./dsdt.o + + #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb + + if ACPI_SSDTX_NUM + makerule ssdt2.c + depends "$(MAINBOARD)/dx/pci2.asl" + action "iasl -tc $(MAINBOARD)/dx/pci2.asl" + action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" + action "mv pci2.hex ssdt2.c" + end + object ./ssdt2.o + makerule ssdt3.c + depends "$(MAINBOARD)/dx/pci3.asl" + action "iasl -tc $(MAINBOARD)/dx/pci3.asl" + action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" + action "mv pci3.hex ssdt3.c" + end + object ./ssdt3.o + makerule ssdt4.c + depends "$(MAINBOARD)/dx/pci4.asl" + action "iasl -tc $(MAINBOARD)/dx/pci4.asl" + action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" + action "mv pci4.hex ssdt4.c" + end + object ./ssdt4.o + makerule ssdt5.c + depends "$(MAINBOARD)/dx/pci5.asl" + action "iasl -tc $(MAINBOARD)/dx/pci5.asl" + action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" + action "mv pci5.hex ssdt5.c" + end + object ./ssdt5.o + end +end + +if USE_DCACHE_RAM + makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c + + if CONFIG_USE_INIT + # compile cache_as_ram.c to auto.o + makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + end + + else + #compile cache_as_ram.c to auto.inc + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" + end + + end +end + +if USE_FAILOVER_IMAGE +else + if CONFIG_AP_CODE_IN_CAR + makerule ./apc_auto.o + depends "$(MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + end + ldscript /arch/i386/init/ldscript_apc.lb + end +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## + +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end +else + if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end +end + +mainboardinit cpu/x86/32bit/entry32.inc +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end +else + if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end +end + + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +if USE_DCACHE_RAM + ## + ## Setup Cache-As-Ram + ## + mainboardinit cpu/amd/car/cache_as_ram.inc +end + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if HAVE_FAILOVER_BOOT + if USE_FAILOVER_IMAGE + if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover_failover.lds + end + end +else + if USE_FALLBACK_IMAGE + if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds + end + end +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +if USE_DCACHE_RAM + + if CONFIG_USE_INIT + initobject cache_as_ram_auto.o + else + mainboardinit ./cache_as_ram_auto.inc + end + +end + +## +## Include the secondary Configuration files +## +if CONFIG_CHIP_NAME + config chip.h +end + +dir /southbridge/amd/amd8151 + +# sample config for amd/serengeti_cheetah_fam10 +chip northbridge/amd/amdfam10/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_F_1207 #L1 and DDR2 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8132 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/i2c/i2cmux2 # pca9556 smbus mux + chip drivers/i2c/i2cmux2 # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + end + end + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end +# device pci 00.5 on end + end + end #pci_domain + #for node 32 to node 63 +# device pci_domain 0 on +# chip northbridge/amd/amdfam10 +# device pci 00.0 on end# northbridge +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.1 on end +# device pci 00.2 on end +# device pci 00.3 on end +# device pci 00.4 on end +# device pci 00.5 on end +# end +# end #pci_domain + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # hard reset +# device pnp 0.9 off end # mcp55 +# device pnp 0.a on end # GH ext table +# end + +end + + |