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-rw-r--r--src/mainboard/amd/quartet/Config.lb27
-rw-r--r--src/mainboard/amd/quartet/auto.c133
-rw-r--r--src/mainboard/amd/quartet/cmos.layout26
-rw-r--r--src/mainboard/amd/quartet/failover.c2
4 files changed, 87 insertions, 101 deletions
diff --git a/src/mainboard/amd/quartet/Config.lb b/src/mainboard/amd/quartet/Config.lb
index d38ab96407..3db696bb7b 100644
--- a/src/mainboard/amd/quartet/Config.lb
+++ b/src/mainboard/amd/quartet/Config.lb
@@ -23,6 +23,12 @@ uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=524288
@@ -45,7 +51,7 @@ default HAVE_HARD_RESET=1
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=7
+default IRQ_SLOT_COUNT=9
##
## Build code to export an x86 MP table
@@ -59,6 +65,13 @@ default HAVE_MP_TABLE=1
default HAVE_OPTION_TABLE=1
##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
## Build code for SMP support
## Only worry about 2 micro processors
##
@@ -73,8 +86,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-#default MAINBOARD_PART_NUMBER="QUARTET"
-#default MAINBOARD_VENDOR="AMD"
+default MAINBOARD_PART_NUMBER="QUARTET"
+default MAINBOARD_VENDOR="AMD"
###
### LinuxBIOS layout values
@@ -163,12 +176,12 @@ makerule ./failover.inc
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h"
+ action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
- action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
+ action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
end
##
@@ -176,6 +189,7 @@ end
##
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
+mainboardinit cpu/i386/bist32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
@@ -334,4 +348,5 @@ end
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
+mainboardinit cpu/i386/bist32_fail.inc
diff --git a/src/mainboard/amd/quartet/auto.c b/src/mainboard/amd/quartet/auto.c
index 475f105b16..35cade92dc 100644
--- a/src/mainboard/amd/quartet/auto.c
+++ b/src/mainboard/amd/quartet/auto.c
@@ -4,14 +4,16 @@
#include <stdint.h>
#include <device/pci_def.h>
-#include <cpu/p6/apic.h>
#include <arch/io.h>
-#include <device/pnp.h>
+#include <device/pnp_def.h>
#include <arch/romcc_io.h>
+#include <arch/smp/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/early_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
@@ -20,8 +22,25 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
+#include "superio/NSC/pc87360/pc87360_early_serial.c"
-#define SIO_BASE 0x2e
+#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
+
+static void hard_reset(void)
+{
+ set_bios_reset();
+ /* enable cf9 */
+ pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+ /* reset */
+ outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+}
+
static void memreset_setup(void)
{
@@ -134,59 +153,6 @@ static void coherent_ht_mainboard(unsigned cpus)
#include "resourcemap.c" /* quartet does not want the default */
-static void enable_lapic(void)
-{
-
- msr_t msr;
- msr = rdmsr(0x1b);
- msr.hi &= 0xffffff00;
- msr.lo &= 0x000007ff;
- msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
- wrmsr(0x1b, msr);
-}
-
-static void stop_this_cpu(void)
-{
- unsigned apicid;
- apicid = apic_read(APIC_ID) >> 24;
-
- /* Send an APIC INIT to myself */
- apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
- apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
- /* Wait for the ipi send to finish */
- apic_wait_icr_idle();
-
- /* Deassert the APIC INIT */
- apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
- apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
- /* Wait for the ipi send to finish */
- apic_wait_icr_idle();
-
- /* If I haven't halted spin forever */
- for(;;) {
- hlt();
- }
-}
-
-#define PC87360_FDC 0x00
-#define PC87360_PP 0x01
-#define PC87360_SP2 0x02
-#define PC87360_SP1 0x03
-#define PC87360_SWC 0x04
-#define PC87360_KBCM 0x05
-#define PC87360_KBCK 0x06
-#define PC87360_GPIO 0x07
-#define PC87360_ACB 0x08
-#define PC87360_FSCM 0x09
-#define PC87360_WDT 0x0A
-
-static void pc87360_enable_serial(void)
-{
- pnp_set_logical_device(SIO_BASE, PC87360_SP1);
- pnp_set_enable(SIO_BASE, 1);
- pnp_set_iobase0(SIO_BASE, 0x3f8);
-}
-
#define RC0 ((1<<1)<<8)
#define RC1 ((1<<2)<<8)
#define RC2 ((1<<3)<<8)
@@ -237,23 +203,31 @@ static void main(void)
.channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
}
};
+ int needs_reset;
+
+ enable_lapic();
+ init_timer();
+
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
- enable_lapic();
- init_timer();
+
+ distinguish_cpu_resets();
+
if (!boot_cpu()) {
-// notify_bsp_ap_is_stopped();
stop_this_cpu();
}
- pc87360_enable_serial();
+
+ pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
setup_quartet_resource_map();
- setup_coherent_ht_domain();
- enumerate_ht_chain(0);
- distinguish_cpu_resets(0);
-
+ needs_reset = setup_coherent_ht_domain();
+ needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+ if (needs_reset) {
+ print_info("ht reset -");
+ soft_reset();
+ }
#if 0
print_pci_devices();
#endif
@@ -270,33 +244,8 @@ static void main(void)
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 2));
#endif
-
- /* Check all of memory */
-#if 0
- msr_t msr;
- msr = rdmsr(TOP_MEM);
- print_debug("TOP_MEM: ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\r\n");
-#endif
-#if 0
- ram_check(0x00000000, msr.lo);
-#endif
-#if 0
- static const struct {
- unsigned long lo, hi;
- } check_addrs[] = {
- /* Check 16MB of memory @ 0*/
- { 0x00000000, 0x01000000 },
#if 0
- /* Check 16MB of memory @ 2GB */
- { 0x80000000, 0x81000000 },
-#endif
- };
- int i;
- for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
- ram_check(check_addrs[i].lo, check_addrs[i].hi);
- }
+ /* Check the first 1M */
+ ram_check(0x00000000, 0x000100000);
#endif
}
diff --git a/src/mainboard/amd/quartet/cmos.layout b/src/mainboard/amd/quartet/cmos.layout
index 5ba4c032c1..247715e6ac 100644
--- a/src/mainboard/amd/quartet/cmos.layout
+++ b/src/mainboard/amd/quartet/cmos.layout
@@ -29,6 +29,9 @@ entries
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
@@ -36,7 +39,14 @@ entries
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 reserved_memory
+
+
enumerations
@@ -66,9 +76,21 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
+8 0 200Mhz
+8 1 166Mhz
+8 2 133Mhz
+8 3 100Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
checksums
-checksum 392 1007 1008
+checksum 392 983 984
diff --git a/src/mainboard/amd/quartet/failover.c b/src/mainboard/amd/quartet/failover.c
index bd9c17020e..e40891b50d 100644
--- a/src/mainboard/amd/quartet/failover.c
+++ b/src/mainboard/amd/quartet/failover.c
@@ -14,7 +14,7 @@ static void main(void)
{
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
- enumerate_ht_chain(0);
+ enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 22:34:40 +0000