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-rw-r--r--src/mainboard/amd/pistachio/romstage.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 6627d747e2..ee00c13df2 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -89,7 +89,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Pistachio used a FPGA to enable serial debug instead of a SIO
* and it doesn't require any special setup. */
- uart_init();
console_init();