2 files changed, 223 insertions, 0 deletions
diff --git a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c
new file mode 100644
index 0000000000..02f83cc1bd
--- /dev/null
+++ b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <amdblocks/agesawrapper.h>
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	/*
+	 * Init Port descriptor (PCIe port, Lanes 8-15,
+	 * PCI Device Number 3, ...)
+	 */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				3, 1,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x02, 0)
+	},
+
+	/*
+	 * Initialize Port descriptor (PCIe port, Lane 7,
+	 * PCI Device Number 2, ...)
+	 */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				2, 5,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x03, 0)
+	},
+	/*
+	 * Initialize Port descriptor (PCIe port, Lane 6,
+	 * PCI Device Number 2, ...)
+	 */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				2, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x04, 0)
+	},
+	/*
+	 * Initialize Port descriptor (PCIe port, Lane 5,
+	 * PCI Device Number 2, ...)
+	 */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
+				2, 3,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x04, 0)
+	},
+	/*
+	 * Initialize Port descriptor (PCIe port, Lane4,
+	 * PCI Device Number 2, ...)
+	 */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				2, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x06, 0)
+	},
+	/*
+	 * Initialize Port descriptor (PCIe port, Lanes 0-3,
+	 * PCI Device Number 2, ...)
+	 */
+	{
+		/*
+		 * Descriptor flags  !!!IMPORTANT!!! Terminate last element
+		 * of array
+		 */
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
+				2, 1,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x07, 0)
+	},
+
+};
+
+
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	/* DP0 */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
+	},
+	/* DP1 */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 20, 23),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+	},
+	/* DP2 */
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
+	},
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = (void *)PortList,
+	.DdiLinkList  = (void *)DdiList
+};
+
+/*---------------------------------------------------------------------------*/
+/**
+ *  OemCustomizeInitEarly
+ *
+ *  Description:
+ *    This is the stub function will call the host environment through the
+ *    binary block interface (call-out port) to provide a user hook opportunity.
+ *
+ *  Parameters:
+ *    @param[in]      **PeiServices
+ *    @param[in]      *InitEarly
+ *
+ *    @retval         VOID
+ *
+ **/
+/*---------------------------------------------------------------------------*/
+VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
+}
diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c
new file mode 100644
index 0000000000..864928732c
--- /dev/null
+++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017-2018 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/southbridge.h>
+#include <amdblocks/lpc.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <drivers/uart/uart8250reg.h>
+#include <arch/io.h>
+#include "../gpio.h"
+
+/* Enable IO access to port, then enable UART HW control pins */
+static void enable_serial(unsigned int base_port, unsigned int io_enable)
+{
+	u32 temp;
+	u8 reg;
+	temp = pci_read_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE);
+	temp |= io_enable;
+	pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, temp);
+
+	/*
+	 * Remove this section if HW handshake is not needed. This is needed
+	 * only for those who don't have a modified serial cable (connecting
+	 * DCD to DTR and DSR, plus connecting RTS to CTS). When you buy cables
+	 * on any store, they don't have these modification.
+	 */
+	reg = inb(base_port + UART8250_MCR);
+	reg |= UART8250_MCR_DTR | UART8250_MCR_RTS;
+	outb(reg, base_port + UART8250_MCR);
+}
+
+void bootblock_mainboard_early_init(void)
+{
+	sb_clk_output_48Mhz(2);
+	/*
+	 * UARTs enabled by default at reset, just need RTS, CTS
+	 * and access to the IO address.
+	 */
+	enable_serial(0x03f8, DECODE_ENABLE_SERIAL_PORT0);
+	enable_serial(0x02f8, DECODE_ENABLE_SERIAL_PORT1);
+}
+
+void bootblock_mainboard_init(void)
+{
+	size_t num_gpios;
+	const struct soc_amd_gpio *gpios;
+
+	gpios = early_gpio_table(&num_gpios);
+	program_gpios(gpios, num_gpios);
+}