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-rw-r--r--src/mainboard/amd/onyx_poc/Kconfig23
-rw-r--r--src/mainboard/amd/onyx_poc/Kconfig.name2
-rw-r--r--src/mainboard/amd/onyx_poc/Makefile.inc11
-rw-r--r--src/mainboard/amd/onyx_poc/board.fmd8
-rw-r--r--src/mainboard/amd/onyx_poc/board_info.txt1
-rw-r--r--src/mainboard/amd/onyx_poc/devicetree.cb203
-rw-r--r--src/mainboard/amd/onyx_poc/dsdt.asl17
-rw-r--r--src/mainboard/amd/onyx_poc/mainboard.c51
8 files changed, 316 insertions, 0 deletions
diff --git a/src/mainboard/amd/onyx_poc/Kconfig b/src/mainboard/amd/onyx_poc/Kconfig
new file mode 100644
index 0000000000..bac8ec80a8
--- /dev/null
+++ b/src/mainboard/amd/onyx_poc/Kconfig
@@ -0,0 +1,23 @@
+if BOARD_AMD_ONYX_POC
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_AMD_GENOA_POC
+ select BOARD_ROMSIZE_KB_32768
+ select AMD_SOC_CONSOLE_UART
+
+config FMDFILE
+ default "src/mainboard/amd/onyx_poc/board.fmd"
+
+
+config MAINBOARD_DIR
+ default "amd/onyx_poc"
+
+config MAINBOARD_PART_NUMBER
+ default "Onyx_poc"
+
+# Use BMC SOL console on SoC UART1 by default
+config UART_FOR_CONSOLE
+ default 1
+
+endif
diff --git a/src/mainboard/amd/onyx_poc/Kconfig.name b/src/mainboard/amd/onyx_poc/Kconfig.name
new file mode 100644
index 0000000000..a896f83696
--- /dev/null
+++ b/src/mainboard/amd/onyx_poc/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_AMD_ONYX_POC
+ bool "Onyx_poc"
diff --git a/src/mainboard/amd/onyx_poc/Makefile.inc b/src/mainboard/amd/onyx_poc/Makefile.inc
new file mode 100644
index 0000000000..323f9ee51e
--- /dev/null
+++ b/src/mainboard/amd/onyx_poc/Makefile.inc
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/Typex60_0_0_0_Apcb.bin),)
+APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/Typex60_0_0_0_Apcb.bin
+APCB_SOURCES1 = $(MAINBOARD_BLOBS_DIR)/Typex60_0_1_0_Apcb.bin
+APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/Typex68_0_0_0_ApcbRec.bin
+APCB_SOURCES_RECOVERY1 = $(MAINBOARD_BLOBS_DIR)/Typex68_0_8_0_ApcbRec.bin
+APCB_SOURCES_RECOVERY2 = $(MAINBOARD_BLOBS_DIR)/Typex68_0_9_0_ApcbRec.bin
+else
+files_added:: warn_no_apcb
+endif
diff --git a/src/mainboard/amd/onyx_poc/board.fmd b/src/mainboard/amd/onyx_poc/board.fmd
new file mode 100644
index 0000000000..a5118c3ef5
--- /dev/null
+++ b/src/mainboard/amd/onyx_poc/board.fmd
@@ -0,0 +1,8 @@
+FLASH 32M {
+ BIOS 16M {
+ COREBOOT(CBFS)
+ FMAP 4K
+ RW_VPD 8K
+ RO_VPD 8K
+ }
+}
diff --git a/src/mainboard/amd/onyx_poc/board_info.txt b/src/mainboard/amd/onyx_poc/board_info.txt
new file mode 100644
index 0000000000..b351b8e696
--- /dev/null
+++ b/src/mainboard/amd/onyx_poc/board_info.txt
@@ -0,0 +1 @@
+Category: eval
diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb
new file mode 100644
index 0000000000..a18eff40da
--- /dev/null
+++ b/src/mainboard/amd/onyx_poc/devicetree.cb
@@ -0,0 +1,203 @@
+chip soc/amd/genoa_poc
+
+ # USB configuration
+ register "usb.xhci0_enable" = "1"
+ register "usb.xhci1_enable" = "1"
+ # OC pins
+ register "usb.usb2_oc_pins[0].port0" = "0x0"
+ register "usb.usb2_oc_pins[0].port1" = "0x1"
+ register "usb.usb2_oc_pins[0].port2" = "0x0"
+ register "usb.usb2_oc_pins[0].port3" = "0x1"
+
+ register "usb.usb2_oc_pins[1].port0" = "0x0"
+ register "usb.usb2_oc_pins[1].port1" = "0x1"
+
+ register "usb.usb3_oc_pins[0].port0" = "0x0"
+ register "usb.usb3_oc_pins[0].port1" = "0x1"
+ register "usb.usb3_oc_pins[0].port2" = "0x0"
+ register "usb.usb3_oc_pins[0].port3" = "0x1"
+ register "usb.usb3_oc_pins[1].port0" = "0x0"
+ register "usb.usb3_oc_pins[1].port1" = "0x1"
+
+ register "usb.polarity_cfg_low" = "true"
+
+ register "usb.usb3_force_gen1.port0" = "3"
+ register "usb.usb3_force_gen1.port1" = "3"
+ register "usb.usb3_force_gen1.port2" = "3"
+ register "usb.usb3_force_gen1.port3" = "3"
+
+ # eSPI configuration
+ register "common_config.espi_config" = "{
+ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN,
+ .io_mode = ESPI_IO_MODE_SINGLE,
+ .op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
+ .crc_check_enable = 1,
+ .alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
+ .periph_ch_en = 0,
+ .vw_ch_en = 0,
+ .oob_ch_en = 0,
+ .flash_ch_en = 0,
+ }"
+
+ # PHY settings
+ register "usb.usb31_phy_enable" = "1"
+ register "usb.usb31_phy" = "{
+ {0x01, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
+ {0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
+ {0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
+ {0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00},
+ {0x05, 0x01, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
+ {0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
+ {0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
+ {0x00, 0x05, 0x07, 0x00, 0x00, 0x07, 0x01, 0x05, 0x00, 0x05, 0x00, 0x05},
+ }"
+
+ device domain 0 on
+ device ref iommu_0 on end
+ device ref rcec_0 on end
+ device ref gpp_bridge_0_0_a on
+ chip vendorcode/amd/opensil/genoa_poc/mpio # P2
+ register "start_lane" = "48"
+ register "end_lane" = "63"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ device generic 0 on end # dummy for configuring mpio
+ end
+ end
+ device ref gpp_bridge_0_0_b on
+ chip vendorcode/amd/opensil/genoa_poc/mpio # G2
+ register "start_lane" = "112"
+ register "end_lane" = "127"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ register "hotplug" = "ServerExpress"
+ device generic 0 on end
+ end
+ end
+ device ref gpp_bridge_0_0_c on
+ chip vendorcode/amd/opensil/genoa_poc/mpio
+ register "start_lane" = "128"
+ register "end_lane" = "131"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ device generic 0 on end
+ end
+ end
+ device ref gpp_bridge_0_a on
+ device ref xhci_0 on end
+ device ref mp0_0 on end
+ end
+ device ref gpp_bridge_0_b on
+ device ref sata_0_0 on end
+ device ref sata_0_1 on end
+ end
+ end
+
+ device domain 1 on
+ device ref iommu_1 on end
+ device ref rcec_1 on end
+ device ref gpp_bridge_1_0_a on
+ chip vendorcode/amd/opensil/genoa_poc/mpio # P3
+ register "start_lane" = "16"
+ register "end_lane" = "31"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ device generic 0 on end
+ end
+ end
+ device ref gpp_bridge_1_0_b on
+ chip vendorcode/amd/opensil/genoa_poc/mpio # G3
+ register "start_lane" = "80"
+ register "end_lane" = "95"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ device generic 0 on end
+ end
+ end
+ end
+
+ device domain 2 on
+ device ref iommu_2 on end
+ device ref rcec_2 on end
+ device ref gpp_bridge_2_0_a on
+ chip vendorcode/amd/opensil/genoa_poc/mpio # P1
+ register "start_lane" = "32"
+ register "end_lane" = "47"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ register "hotplug" = "ServerExpress"
+ device generic 0 on end
+ end
+ end
+ device ref gpp_bridge_2_0_b on
+ chip vendorcode/amd/opensil/genoa_poc/mpio # G1
+ register "start_lane" = "64"
+ register "end_lane" = "79"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ device generic 0 on end
+ end
+ end
+
+ end
+
+ device domain 3 on
+ device ref iommu_3 on end
+ device ref rcec_3 on end
+ device ref gpp_bridge_3_0_a on
+ chip vendorcode/amd/opensil/genoa_poc/mpio # P0
+ register "start_lane" = "0"
+ register "end_lane" = "15"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ device generic 0 on end
+ end
+ end
+ device ref gpp_bridge_3_0_b on
+ chip vendorcode/amd/opensil/genoa_poc/mpio # G0
+ register "start_lane" = "96"
+ register "end_lane" = "111"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ device generic 0 on end
+ end
+ end
+ device ref gpp_bridge_3_0_c on # WAFL
+ chip vendorcode/amd/opensil/genoa_poc/mpio
+ register "start_lane" = "132"
+ register "end_lane" = "133"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ device generic 0 on end
+ end
+ end
+ device ref gpp_bridge_3_1_c on # BMC
+ chip vendorcode/amd/opensil/genoa_poc/mpio
+ register "start_lane" = "134"
+ register "end_lane" = "134"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ register "bmc" = "1"
+ device generic 0 on end
+ end
+ end
+ device ref gpp_bridge_3_2_c on # BMC
+ chip vendorcode/amd/opensil/genoa_poc/mpio
+ register "start_lane" = "135"
+ register "end_lane" = "135"
+ register "gpio_group" = "1"
+ register "aspm" = "L1"
+ device generic 0 on end
+ end
+ end
+ device ref gpp_bridge_3_a on
+ device ref xhci_3 on end
+ device ref mp0_3 on end
+ end
+ device ref gpp_bridge_3_b on
+ device ref sata_3_0 on end
+ device ref sata_3_1 on end
+ end
+ end
+
+end
diff --git a/src/mainboard/amd/onyx_poc/dsdt.asl b/src/mainboard/amd/onyx_poc/dsdt.asl
new file mode 100644
index 0000000000..caaf131732
--- /dev/null
+++ b/src/mainboard/amd/onyx_poc/dsdt.asl
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* DefinitionBlock Statement */
+#include <acpi/acpi.h>
+DefinitionBlock (
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x00010001 /* OEM Revision */
+)
+{ /* Start of ASL file */
+ #include <acpi/dsdt_top.asl>
+
+ #include <soc.asl>
+} /* End of ASL file */
diff --git a/src/mainboard/amd/onyx_poc/mainboard.c b/src/mainboard/amd/onyx_poc/mainboard.c
new file mode 100644
index 0000000000..af89e140b1
--- /dev/null
+++ b/src/mainboard/amd/onyx_poc/mainboard.c
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/acpi.h>
+#include <soc/amd_pci_int_defs.h>
+#include <amdblocks/amd_pci_util.h>
+#include <types.h>
+
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
+
+/*
+ * This controls the device -> IRQ routing.
+ *
+ * Hardcoded IRQs:
+ * 0: timer < soc/amd/common/acpi/lpc.asl
+ * 1: i8042 - Keyboard
+ * 2: cascade
+ * 8: rtc0 <- soc/amd/common/acpi/lpc.asl
+ * 9: acpi <- soc/amd/common/acpi/lpc.asl
+ */
+static const struct fch_irq_routing fch_irq_map[] = {
+ { PIRQ_A, 12, PIRQ_NC },
+ { PIRQ_B, 14, PIRQ_NC },
+ { PIRQ_C, 15, PIRQ_NC },
+ { PIRQ_D, 12, PIRQ_NC },
+ { PIRQ_E, 14, PIRQ_NC },
+ { PIRQ_F, 15, PIRQ_NC },
+ { PIRQ_G, 12, PIRQ_NC },
+ { PIRQ_H, 14, PIRQ_NC },
+
+ { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
+ { PIRQ_GPIO, 11, 11 },
+ { PIRQ_I2C0, 10, 10 },
+ { PIRQ_I2C1, 7, 7 },
+ { PIRQ_I2C2, 6, 6 },
+ { PIRQ_I2C3, 5, 5 },
+ { PIRQ_UART0, 4, 4 },
+ { PIRQ_UART1, 3, 3 },
+
+ /* The MISC registers are not interrupt numbers */
+ { PIRQ_MISC, 0xfa, 0x00 },
+ { PIRQ_MISC0, 0x91, 0x00 },
+ { PIRQ_HPET_L, 0x00, 0x00 },
+ { PIRQ_HPET_H, 0x00, 0x00 },
+};
+
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+{
+ *length = ARRAY_SIZE(fch_irq_map);
+ return fch_irq_map;
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 15:25:07 +0000