summaryrefslogtreecommitdiff
path: root/src/mainboard/amd/majolica
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/amd/majolica')
-rw-r--r--src/mainboard/amd/majolica/Kconfig15
-rw-r--r--src/mainboard/amd/majolica/chromeos.fmd40
2 files changed, 45 insertions, 10 deletions
diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig
index ef0aa2048b..6f3f93ba30 100644
--- a/src/mainboard/amd/majolica/Kconfig
+++ b/src/mainboard/amd/majolica/Kconfig
@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_16384
select SOC_AMD_CEZANNE
select AMD_SOC_CONSOLE_UART
+ select MAINBOARD_HAS_CHROMEOS
config FMDFILE
string
@@ -21,6 +22,7 @@ config MAINBOARD_PART_NUMBER
config AMD_FWM_POSITION_INDEX
int
+ default 3 if CHROMEOS
default 4
help
TODO: might need to be adapted for better placement of files in cbfs
@@ -37,4 +39,17 @@ config MAJOLICA_MCHP_FW_FILE
The EC firmware blob is usually the first 128kByte of the stock
firmware image.
+config VBOOT
+ select VBOOT_NO_BOARD_SUPPORT
+ select VBOOT_SEPARATE_VERSTAGE
+ select VBOOT_STARTS_IN_BOOTBLOCK
+
+config VBOOT_VBNV_OFFSET
+ hex
+ default 0x2A
+
+config CHROMEOS
+ # Use default libpayload config
+ select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
+
endif # BOARD_AMD_MAJOLICA
diff --git a/src/mainboard/amd/majolica/chromeos.fmd b/src/mainboard/amd/majolica/chromeos.fmd
index 90cf2eb879..bb21767c31 100644
--- a/src/mainboard/amd/majolica/chromeos.fmd
+++ b/src/mainboard/amd/majolica/chromeos.fmd
@@ -1,14 +1,34 @@
FLASH@0xFF000000 16M {
- BIOS {
+ SI_BIOS {
EC 128K
- RW_MRC_CACHE 64K
- RW_LEGACY(CBFS) 4K
- FW_MAIN_A(CBFS) 1M
- VBLOCK_A 8K
- FW_MAIN_B(CBFS) 1M
- VBLOCK_B 8K
- SHARED_DATA 8K
- FMAP 4K
- COREBOOT(CBFS)
+ RW_MRC_CACHE(PRESERVE) 64K
+ RW_SECTION_A 3M {
+ VBLOCK_A 8K
+ FW_MAIN_A(CBFS)
+ RW_FWID_A 256
+ }
+ RW_SECTION_B 3M {
+ VBLOCK_B 8K
+ FW_MAIN_B(CBFS)
+ RW_FWID_B 256
+ }
+ RW_ELOG(PRESERVE) 4K
+ RW_SHARED 16K {
+ SHARED_DATA 8K
+ VBLOCK_DEV 8K
+ }
+ RW_VPD(PRESERVE) 8K
+ RW_NVRAM(PRESERVE) 20K
+ SMMSTORE(PRESERVE) 4K
+ RW_LEGACY(CBFS)
+ WP_RO@8M 8M {
+ RO_VPD(PRESERVE) 16K
+ RO_SECTION {
+ FMAP 2K
+ RO_FRID 64
+ GBB@4K 448K
+ COREBOOT(CBFS)
+ }
+ }
}
}