aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/amd/mahogany_fam10/romstage.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/amd/mahogany_fam10/romstage.c')
-rw-r--r--src/mainboard/amd/mahogany_fam10/romstage.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index ebb47f1cdc..eb0adc5fc8 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -58,14 +58,12 @@ static void post_code(u8 value) {
outb(value, 0x80);
}
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
#include "arch/i386/lib/console.c"
#include "pc80/serial.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
-#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
@@ -80,8 +78,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
#include "cpu/x86/bist.h"
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
-
static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8718f/it8718f_early_serial.c"
@@ -128,13 +124,10 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/fidvid.c"
-#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
-
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
-#if (CONFIG_USE_FAILOVER_IMAGE==0)
//#include "spd_addr.h"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
@@ -306,5 +299,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x43); // Should never see this post code.
}
-
-#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */