1 files changed, 139 insertions, 0 deletions
diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
index 055d9e15e2..58c022ec0e 100644
--- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
+++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
@@ -41,6 +41,145 @@ chip soc/amd/phoenix
 
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
 
+	register "usb_phy_custom" = "1"
+	register "usb_phy" = "{
+		.Usb2PhyPort[0] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[1] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[2] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[3] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[4] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[5] = {
+			.compdistune = 0x1,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[6] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x6,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[7] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xc,
+			.sqrxtune = 0x2,
+			.txfslstune = 0x1,
+			.txpreempamptune = 0x3,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x6,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb3PhyPort[0] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.Usb3PhyPort[1] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.Usb3PhyPort[2] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
+		.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
+		.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
+		.BatteryChargerEnable = 0,
+		.PhyP3CpmP4Support = 0,
+	}"
+
 	register "ddi[0]" = "{
 		.connector_type = DDI_EDP,
 		.aux_index = 0,