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-rw-r--r--src/include/device/sd_mmc_ctrlr.h228
-rw-r--r--src/include/device/sdhci.h76
-rw-r--r--src/include/device/storage.h151
3 files changed, 0 insertions, 455 deletions
diff --git a/src/include/device/sd_mmc_ctrlr.h b/src/include/device/sd_mmc_ctrlr.h
deleted file mode 100644
index 2ca2d0f19a..0000000000
--- a/src/include/device/sd_mmc_ctrlr.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * Copyright 2011, Marvell Semiconductor Inc.
- * Lei Wen <leiwen@marvell.com>
- *
- * Copyright 2017 Intel Corporation
- *
- * Controller independent definitions
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef __DEVICE_SD_MMC_CTRLR_H__
-#define __DEVICE_SD_MMC_CTRLR_H__
-
-#include <stdint.h>
-
-/* Error values returned by the storage drivers */
-#define CARD_UNUSABLE_ERR -17 /* Unusable Card */
-#define CARD_COMM_ERR -18 /* Communications Error */
-#define CARD_TIMEOUT -19
-#define CARD_IN_PROGRESS -20 /* operation is in progress */
-
-struct mmc_command {
- uint16_t cmdidx;
-
-/* Common commands */
-#define MMC_CMD_GO_IDLE_STATE 0
-#define MMC_CMD_SEND_OP_COND 1
-#define MMC_CMD_ALL_SEND_CID 2
-#define MMC_CMD_SET_DSR 4
-#define MMC_CMD_SELECT_CARD 7
-#define MMC_CMD_SEND_CSD 9
-#define MMC_CMD_SEND_CID 10
-#define MMC_CMD_STOP_TRANSMISSION 12
-#define MMC_CMD_SEND_STATUS 13
-#define MMC_CMD_SET_BLOCKLEN 16
-#define MMC_CMD_READ_SINGLE_BLOCK 17
-#define MMC_CMD_READ_MULTIPLE_BLOCK 18
-#define MMC_CMD_WRITE_SINGLE_BLOCK 24
-#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
-#define MMC_CMD_APP_CMD 55
-
-/* MMC specific commands */
-#define MMC_CMD_SET_RELATIVE_ADDR 3
-#define MMC_CMD_SWITCH 6
-#define MMC_CMD_SEND_EXT_CSD 8
-#define MMC_CMD_AUTO_TUNING_SEQUENCE 21
-#define MMC_CMD_ERASE_GROUP_START 35
-#define MMC_CMD_ERASE_GROUP_END 36
-#define MMC_CMD_ERASE 38
-#define MMC_CMD_SPI_READ_OCR 58
-#define MMC_CMD_SPI_CRC_ON_OFF 59
-
-/* SD specific commands */
-#define SD_CMD_SEND_RELATIVE_ADDR 3
-#define SD_CMD_SWITCH_FUNC 6
-#define SD_CMD_SEND_IF_COND 8
-#define SD_CMD_ERASE_WR_BLK_START 32
-#define SD_CMD_ERASE_WR_BLK_END 33
-
-/* SD specific APP commands */
-#define SD_CMD_APP_SET_BUS_WIDTH 6
-#define SD_CMD_APP_SEND_OP_COND 41
-#define SD_CMD_APP_SEND_SCR 51
-
- uint32_t resp_type;
-
-#define CARD_RSP_PRESENT (1 << 0)
-#define CARD_RSP_136 (1 << 1) /* 136 bit response */
-#define CARD_RSP_CRC (1 << 2) /* expect valid crc */
-#define CARD_RSP_BUSY (1 << 3) /* card may send busy */
-#define CARD_RSP_OPCODE (1 << 4) /* response contains opcode */
-
-#define CARD_RSP_NONE (0)
-#define CARD_RSP_R1 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
-#define CARD_RSP_R1b (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE| \
- CARD_RSP_BUSY)
-#define CARD_RSP_R2 (CARD_RSP_PRESENT|CARD_RSP_136|CARD_RSP_CRC)
-#define CARD_RSP_R3 (CARD_RSP_PRESENT)
-#define CARD_RSP_R4 (CARD_RSP_PRESENT)
-#define CARD_RSP_R5 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
-#define CARD_RSP_R6 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
-#define CARD_RSP_R7 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
-
- uint32_t cmdarg;
-
-#define MMC_TRIM_ARG 0x1
-#define MMC_SECURE_ERASE_ARG 0x80000000
-
- uint32_t response[4];
- uint32_t flags;
-
-#define CMD_FLAG_IGNORE_INHIBIT 1
-};
-
-#define SD_SWITCH_CHECK 0
-#define SD_SWITCH_SWITCH 1
-
-#define SD_DATA_4BIT 0x00040000
-
-/* SCR definitions in different words */
-#define SD_HIGHSPEED_BUSY 0x00020000
-#define SD_HIGHSPEED_SUPPORTED 0x00020000
-
-struct mmc_data {
- union {
- char *dest;
- const char *src;
- };
- uint32_t flags;
-
-#define DATA_FLAG_READ 1
-#define DATA_FLAG_WRITE 2
-
- uint32_t blocks;
- uint32_t blocksize;
-};
-
-struct sd_mmc_ctrlr {
- int (*send_cmd)(struct sd_mmc_ctrlr *ctrlr,
- struct mmc_command *cmd, struct mmc_data *data);
- void (*set_ios)(struct sd_mmc_ctrlr *ctrlr);
- void (*tuning_start)(struct sd_mmc_ctrlr *ctrlr, int retune);
- int (*is_tuning_complete)(struct sd_mmc_ctrlr *ctrlr, int *successful);
-
- int initialized;
- unsigned int version;
- uint32_t voltages;
-
-#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
-#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
-#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
-#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
-#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
-#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
-#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
-#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
-#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
-#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
-#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
-#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
-#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
-#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
-#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
-#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
-#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
-
-#define MMC_VDD_165_195_SHIFT 7
-
- uint32_t clock_base; /* Controller's base clock */
- uint32_t f_min;
- uint32_t f_max;
- uint32_t request_hz; /* Desired clock frequency */
- uint32_t bus_hz; /* Actual bus clock frequency */
-
-#define CLOCK_KHZ 1000
-#define CLOCK_MHZ (1000 * CLOCK_KHZ)
-#define CLOCK_20MHZ (20 * CLOCK_MHZ)
-#define CLOCK_25MHZ (25 * CLOCK_MHZ)
-#define CLOCK_26MHZ (26 * CLOCK_MHZ)
-#define CLOCK_50MHZ (50 * CLOCK_MHZ)
-#define CLOCK_52MHZ (52 * CLOCK_MHZ)
-#define CLOCK_200MHZ (200 * CLOCK_MHZ)
-
- uint32_t bus_width;
- uint32_t caps;
-
-/* Generic controller & driver capabilities. Controller specific capabilities
- * start at 0x00010000
- */
-#define DRVR_CAP_4BIT 0x00000001
-#define DRVR_CAP_8BIT 0x00000002
-#define DRVR_CAP_AUTO_CMD12 0x00000004
-#define DRVR_CAP_HC 0x00000008
-#define DRVR_CAP_HS 0x00000010
-#define DRVR_CAP_HS52 0x00000020
-#define DRVR_CAP_HS200 0x00000040
-#define DRVR_CAP_HS400 0x00000080
-#define DRVR_CAP_ENHANCED_STROBE 0x00000100
-#define DRVR_CAP_REMOVABLE 0x00000200
-#define DRVR_CAP_DMA_64BIT 0x00000400
-#define DRVR_CAP_HS200_TUNING 0x00000800
-
- uint32_t b_max;
- uint32_t timing;
-
-#define BUS_TIMING_LEGACY 0
-#define BUS_TIMING_MMC_HS 1
-#define BUS_TIMING_SD_HS 2
-#define BUS_TIMING_UHS_SDR12 3
-#define BUS_TIMING_UHS_SDR25 4
-#define BUS_TIMING_UHS_SDR50 5
-#define BUS_TIMING_UHS_SDR104 6
-#define BUS_TIMING_UHS_DDR50 7
-#define BUS_TIMING_MMC_DDR52 8
-#define BUS_TIMING_MMC_HS200 9
-#define BUS_TIMING_MMC_HS400 10
-#define BUS_TIMING_MMC_HS400ES 11
-
- uint32_t mdelay_before_cmd0;
- uint32_t mdelay_after_cmd0;
- uint32_t udelay_wait_after_cmd;
-};
-
-/* SOC specific routine to override ctrlr->caps and .voltages
- *
- * Set/clear the necessary DRVR_CAP_xxx bits in ctrlr->caps to specify the
- * controllers capabilities and driver workarounds.
- *
- * Set/clear the necessary MMC_VDD_xxx bits in ctrlr->voltages to specify the
- * controllers power support.
- */
-void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr);
-
-/* Optional routines to support logging */
-void sdhc_log_command(struct mmc_command *cmd);
-void sdhc_log_command_issued(void);
-void sdhc_log_response(uint32_t entries, uint32_t *response);
-void sdhc_log_ret(int ret);
-
-#endif /* __DEVICE_SD_MMC_CTRLR_H__ */
diff --git a/src/include/device/sdhci.h b/src/include/device/sdhci.h
deleted file mode 100644
index a86582d767..0000000000
--- a/src/include/device/sdhci.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright 2011, Marvell Semiconductor Inc.
- * Lei Wen <leiwen@marvell.com>
- *
- * Copyright 2017 Intel Corporation
- *
- * SD host controller specific definitions
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef __DEVICE_SDHCI_H__
-#define __DEVICE_SDHCI_H__
-
-#include <device/sd_mmc_ctrlr.h>
-
-/* Driver specific capabilities */
-#define DRVR_CAP_1V8_VDD 0x00010000
-#define DRVR_CAP_32BIT_DMA_ADDR 0x00020000
-#define DRVR_CAP_BROKEN_R1B 0x00040000
-#define DRVR_CAP_NO_CD 0x00080000
-#define DRVR_CAP_NO_HISPD_BIT 0x00100000
-#define DRVR_CAP_NO_SIMULT_VDD_AND_POWER 0x00200000
-#define DRVR_CAP_REG32_RW 0x00400000
-#define DRVR_CAP_SPI 0x00800000
-#define DRVR_CAP_WAIT_SEND_CMD 0x01000000
-
-/* ADMA packet descriptor */
-struct sdhci_adma {
- u16 attributes;
- u16 length;
- u32 addr;
-};
-
-struct sdhci_adma64 {
- u16 attributes;
- u16 length;
- u32 addr;
- u32 addr_hi;
-};
-
-struct sdhci_ctrlr {
- struct sd_mmc_ctrlr sd_mmc_ctrlr;
- void *ioaddr;
- uint32_t b_max;
-
- /*
- * Dynamically allocated array of ADMA descriptors to use for data
- * transfers
- */
- struct sdhci_adma *adma_descs;
- struct sdhci_adma64 *adma64_descs;
-
- /* Number of ADMA descriptors currently in the array. */
- int adma_desc_count;
-};
-
-int add_sdhci(struct sdhci_ctrlr *sdhci_ctrlr);
-int sdhci_controller_init(struct sdhci_ctrlr *sdhci_ctrlr, void *ioaddr);
-void sdhci_update_pointers(struct sdhci_ctrlr *sdhci_ctrlr);
-void sdhci_display_setup(struct sdhci_ctrlr *sdhci_ctrlr);
-
-/* Add SDHCI controller from PCI */
-struct sd_mmc_ctrlr *new_pci_sdhci_controller(uint32_t dev);
-
-/* Add SDHCI controller with memory address */
-struct sd_mmc_ctrlr *new_mem_sdhci_controller(void *ioaddr);
-
-#endif /* __DEVICE_SDHCI_H__ */
diff --git a/src/include/device/storage.h b/src/include/device/storage.h
deleted file mode 100644
index ef7e0ff6e0..0000000000
--- a/src/include/device/storage.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright 2008,2010 Freescale Semiconductor, Inc
- * Andy Fleming
- *
- * Copyright 2013 Google Inc. All rights reserved.
- * Copyright 2017 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __DEVICE_STORAGE_H__
-#define __DEVICE_STORAGE_H__
-
-#include <device/sd_mmc_ctrlr.h>
-
-/*
- * EXT_CSD fields
- */
-#define EXT_CSD_GP_SIZE_MULT_GP0 143 /* RO */
-#define EXT_CSD_GP_SIZE_MULT_GP1 146 /* RO */
-#define EXT_CSD_GP_SIZE_MULT_GP2 149 /* RO */
-#define EXT_CSD_GP_SIZE_MULT_GP3 152 /* RO */
-#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
-#define EXT_CSD_RPMB_SIZE_MULT 168 /* RO */
-#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
-#define EXT_CSD_PART_CONF 179 /* R/W */
-#define EXT_CSD_BUS_WIDTH 183 /* R/W */
-#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
-#define EXT_CSD_HS_TIMING 185 /* R/W */
-#define EXT_CSD_REV 192 /* RO */
-#define EXT_CSD_CARD_TYPE 196 /* RO */
-#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
-#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
-#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
-#define EXT_CSD_BOOT_SIZE_MULT 226 /* RO */
-#define EXT_CSD_TRIM_MULT 232 /* RO */
-
-/*
- * EXT_CSD field definitions
- */
-
-#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
-#define EXT_CSD_CMD_SET_SECURE (1 << 1)
-#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
-
-#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
-
-#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
-#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
-#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
-#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
-#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
-#define EXT_CSD_BUS_WIDTH_STROBE (1<<7) /* Enhanced strobe mode */
-
-#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
-#define EXT_CSD_TIMING_HS 1 /* High speed */
-#define EXT_CSD_TIMING_HS200 2 /* HS200 */
-#define EXT_CSD_TIMING_HS400 3 /* HS400 */
-
-#define EXT_CSD_SIZE 512
-
-/* 179: EXT_CSD_PART_CONF */
-#define EXT_CSD_PART_ACCESS_MASK 7 /* Partition access mask */
-
-/* 175: EXT_CSD_ERASE_GROUP_DEF */
-#define EXT_CSD_PARTITION_ENABLE 1 /* Enable partition access */
-
-struct storage_media {
- uint64_t capacity[8]; /* Partition capacity in bytes */
- struct sd_mmc_ctrlr *ctrlr;
-
-#define MMC_PARTITION_USER 0
-#define MMC_PARTITION_BOOT_1 1
-#define MMC_PARTITION_BOOT_2 2
-#define MMC_PARTITION_RPMB 3
-#define MMC_PARTITION_GP1 4
-#define MMC_PARTITION_GP2 5
-#define MMC_PARTITION_GP3 6
-#define MMC_PARTITION_GP4 7
-
- uint32_t caps;
- uint32_t version;
-
-#define SD_VERSION_SD 0x20000
-#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
-#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
-#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
-#define MMC_VERSION_MMC 0x10000
-#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
-#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
-#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
-#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
-#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
-#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
-
- uint32_t read_bl_len;
- uint32_t write_bl_len;
- int high_capacity;
- uint32_t tran_speed;
- /* Erase size in terms of block length. */
- uint32_t erase_blocks;
- /* Trim operation multiplier for determining timeout. */
- uint32_t trim_mult;
-
- uint32_t ocr;
-
-#define OCR_BUSY 0x80000000
-#define OCR_HCS 0x40000000
-#define OCR_VOLTAGE_MASK 0x00FFFF80
-#define OCR_ACCESS_MODE 0x60000000
-
- uint32_t op_cond_response; // The response byte from the last op_cond
-
- uint32_t scr[2];
- uint32_t csd[4];
- uint32_t cid[4];
- uint16_t rca;
-
- uint8_t partition_config; /* Duplicate of EXT_CSD_PART_CONF */
-};
-
-uint64_t storage_block_erase(struct storage_media *media, uint64_t start,
- uint64_t count);
-uint64_t storage_block_fill_write(struct storage_media *media, uint64_t start,
- uint64_t count, uint32_t fill_pattern);
-uint64_t storage_block_read(struct storage_media *media, uint64_t start,
- uint64_t count, void *buffer);
-uint64_t storage_block_write(struct storage_media *media, uint64_t start,
- uint64_t count, const void *buffer);
-
-unsigned int storage_get_current_partition(struct storage_media *media);
-const char *storage_partition_name(struct storage_media *media,
- unsigned int partition_number);
-int storage_setup_media(struct storage_media *media,
- struct sd_mmc_ctrlr *ctrlr);
-
-int storage_set_partition(struct storage_media *media,
- unsigned int partition_number);
-
-void storage_display_setup(struct storage_media *media);
-
-#endif /* __DEVICE_STORAGE_H__ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 01:46:05 +0000