diff options
Diffstat (limited to 'src/drivers/intel/fsp2_0')
| -rw-r--r-- | src/drivers/intel/fsp2_0/memory_init.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 4f0dbf6148..6d25844b50 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -24,8 +24,8 @@ #include <types.h> #include <vb2_api.h> -#if CONFIG(SOC_INTEL_COMMON_BASECODE_TOM) -#include <intelbasecode/tom.h> +#if CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP) +#include <intelbasecode/ramtop.h> #endif static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); @@ -259,10 +259,10 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) die_with_post_code(POST_INVALID_VENDOR_BINARY, "FSPM_ARCH_UPD not found!\n"); - /* Early caching of TOM region if valid mrc cache data is found */ -#if (CONFIG(SOC_INTEL_COMMON_BASECODE_TOM)) + /* Early caching of RAMTOP region if valid mrc cache data is found */ +#if (CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP)) if (arch_upd->NvsBufferPtr) - early_tom_enable_cache_range(); + early_ramtop_enable_cache_range(); #endif /* Give SoC and mainboard a chance to update the UPD */ |