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-rw-r--r--src/cpu/samsung/exynos5250/Makefile.inc1
-rw-r--r--src/cpu/samsung/exynos5250/exynos_cache.c11
2 files changed, 0 insertions, 12 deletions
diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc
index 2774b12c28..961b719505 100644
--- a/src/cpu/samsung/exynos5250/Makefile.inc
+++ b/src/cpu/samsung/exynos5250/Makefile.inc
@@ -30,7 +30,6 @@ ramstage-y += power.c
ramstage-y += soc.c
ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
ramstage-y += cpu.c
-ramstage-y += exynos_cache.c
#ramstage-$(CONFIG_SATA_AHCI) += sata.c
diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c
index 7f4effe3a0..2cb918d357 100644
--- a/src/cpu/samsung/exynos5250/exynos_cache.c
+++ b/src/cpu/samsung/exynos5250/exynos_cache.c
@@ -33,17 +33,6 @@ enum l2_cache_params {
CACHE_DATA_RAM_LATENCY = (2<<0)
};
-
-/* FIXME(dhendrix): maybe move this to a romstage-specific file? */
-#ifdef __PRE_RAM__
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- /* can't use it anyway -- it has dependencies we have to fix. */
- //dcache_enable();
-}
-#endif
-
/*
* Set L2 cache parameters
*/