diff options
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram_ht.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 5 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 5 |
5 files changed, 1 insertions, 21 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 781e48017b..1ea50b8b37 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -357,17 +357,12 @@ lout: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run .Lhlt: diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 9ef69adfcb..8a845e954a 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -431,17 +431,12 @@ no_msr_11e: post_code(0x3c) - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run .Lhlt: diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 077e409a5e..1093e6b1e5 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -326,7 +326,7 @@ void romstage_after_car(void) #endif /* Load the ramstage. */ - copy_and_run(0); + copy_and_run(); } diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 4202da9800..2652cb7433 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -316,17 +316,12 @@ __acpi_resume_backup_done: post_code(0x3d) - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run .Lhlt: diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index b8222e15a2..50fab35ccc 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -225,17 +225,12 @@ clear_mtrrs: post_code(0x3c) - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi call copy_and_run .Lhlt: |