3 files changed, 50 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
new file mode 100644
index 0000000000..dfb3181096
--- /dev/null
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -0,0 +1,28 @@
+config CPU_INTEL_SOCKET_LGA775
+	bool
+
+if CPU_INTEL_SOCKET_LGA775
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select CPU_INTEL_MODEL_6EX
+	select CPU_INTEL_MODEL_6FX
+	select CPU_INTEL_MODEL_F3X
+	select CPU_INTEL_MODEL_F4X
+#	select CPU_INTEL_MODEL_F6X
+#	select CPU_INTEL_MODEL_1066X
+	select CPU_INTEL_MODEL_1067X
+	select MMX
+	select SSE
+	select UDELAY_TSC
+	select SIPI_VECTOR_IN_ROM
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x4000 # 16 kB
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE
+
+endif # CPU_INTEL_SOCKET_LGA775
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
new file mode 100644
index 0000000000..100b4d8e93
--- /dev/null
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -0,0 +1,17 @@
+ramstage-y += socket_LGA775.c
+subdirs-y += ../model_6ex
+subdirs-y += ../model_6fx
+subdirs-y += ../model_f3x
+subdirs-y += ../model_f4x
+#subdirs-y += ../model_f6x
+#subdirs-y += ../model_1066x
+subdirs-y += ../model_1067x
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+
+cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc
diff --git a/src/cpu/intel/socket_LGA775/socket_LGA775.c b/src/cpu/intel/socket_LGA775/socket_LGA775.c
new file mode 100644
index 0000000000..7ec4e5e4b6
--- /dev/null
+++ b/src/cpu/intel/socket_LGA775/socket_LGA775.c
@@ -0,0 +1,5 @@
+#include <device/device.h>
+
+struct chip_operations cpu_intel_socket_LGA775_ops = {
+	CHIP_NAME("Socket LGA775 CPU")
+};