4 files changed, 37 insertions, 35 deletions
diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig
index 96c7040706..b572385b4f 100644
--- a/src/cpu/intel/model_6xx/Kconfig
+++ b/src/cpu/intel/model_6xx/Kconfig
@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_6XX
 	bool
 	select SMP
+	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 5fdd71c55b..0c41cf2487 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1 +1,3 @@
 ramstage-y += model_6xx_init.c
+
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
new file mode 100644
index 0000000000..8a7ef26c93
--- /dev/null
+++ b/src/cpu/intel/model_6xx/microcode_blob.c
@@ -0,0 +1,33 @@
+unsigned microcode_updates_6xx[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+
+#include "microcode-99-B_c6_612.h"
+#include "microcode-43-B_c6_617.h"
+#include "microcode-51-B_c6_616.h"
+#include "microcode-153-d2_619.h"
+
+#include "microcode-308-MU163336.h"
+#include "microcode-309-MU163437.h"
+
+#include "microcode-358-MU166d05.h"
+#include "microcode-359-MU166d06.h"
+#include "microcode-386-MU16600a.h"
+#include "microcode-398-MU166503.h"
+#include "microcode-399-MU166a0b.h"
+#include "microcode-400-MU166a0c.h"
+#include "microcode-401-MU166a0d.h"
+#include "microcode-402-MU166d07.h"
+
+#include "microcode-566-mu26a003.h"
+#include "microcode-588-mu26a101.h"
+#include "microcode-620-MU26a401.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index 5724add4e8..e81f9aebe8 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -9,40 +9,6 @@
 #include <cpu/intel/microcode.h>
 #include <cpu/x86/cache.h>
 
-static uint32_t microcode_updates[] = {
-	/* WARNING - Intel has a new data structure that has variable length
-	 * microcode update lengths.  They are encoded in int 8 and 9.  A
-	 * dummy header of nulls must terminate the list.
-	 */
-
-#include "microcode-99-B_c6_612.h"
-#include "microcode-43-B_c6_617.h"
-#include "microcode-51-B_c6_616.h"
-#include "microcode-153-d2_619.h"
-
-#include "microcode-308-MU163336.h"
-#include "microcode-309-MU163437.h"
-
-#include "microcode-358-MU166d05.h"
-#include "microcode-359-MU166d06.h"
-#include "microcode-386-MU16600a.h"
-#include "microcode-398-MU166503.h"
-#include "microcode-399-MU166a0b.h"
-#include "microcode-400-MU166a0c.h"
-#include "microcode-401-MU166a0d.h"
-#include "microcode-402-MU166d07.h"
-
-#include "microcode-566-mu26a003.h"
-#include "microcode-588-mu26a101.h"
-#include "microcode-620-MU26a401.h"
-
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
 static void model_6xx_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
@@ -51,7 +17,7 @@ static void model_6xx_init(device_t dev)
 	x86_mtrr_check();
 
 	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	intel_update_microcode_from_cbfs();
 
 	/* Enable the local cpu apics */
 	setup_lapic();