diff options
Diffstat (limited to 'src/cpu/intel/model_206ax/cache_as_ram.inc')
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 33246ff5bb..9a2db37ef4 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -259,17 +259,19 @@ before_romstage: movl $CPU_PHYSMASK_HI, %edx // 36bit address space wrmsr +#if CONFIG_CACHE_ROM_SIZE /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif post_code(0x39) |