diff options
Diffstat (limited to 'src/cpu/intel/model_2065x/finalize.c')
| -rw-r--r-- | src/cpu/intel/model_2065x/finalize.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index b37a84cfe7..1835dce3db 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -25,6 +25,11 @@ #include <cpu/intel/speedstep.h> #include "model_2065x.h" +/* MSR Documentation based on + * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)" + * Document Number 504790 + * Revision 1.6.0, June 2012 */ + static void msr_set_bit(unsigned reg, unsigned bit) { msr_t msr = rdmsr(reg); @@ -44,6 +49,7 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_2065x_finalize_smm(void) { + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ @@ -67,7 +73,9 @@ void intel_model_2065x_finalize_smm(void) msr_set_bit(MSR_PP0_POWER_LIMIT, 31); msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif - + /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } |