aboutsummaryrefslogtreecommitdiff
path: root/src/cpu/intel/haswell/haswell.h
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/intel/haswell/haswell.h')
-rw-r--r--src/cpu/intel/haswell/haswell.h17
1 files changed, 0 insertions, 17 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 23efe6c443..8498c1ac75 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -163,24 +163,7 @@ struct romstage_params {
unsigned long bist;
void (*copy_spd)(struct pei_data *);
};
-void mainboard_romstage_entry(unsigned long bist);
void romstage_common(const struct romstage_params *params);
-/* romstage_main is called from the cache-as-ram assembly file. The return
- * value is the stack value to be used for romstage once cache-as-ram is
- * torn down. The following values are pushed onto the stack to setup the
- * MTRRs:
- * +0: Number of MTRRs
- * +4: MTRR base 0 31:0
- * +8: MTRR base 0 63:32
- * +12: MTRR mask 0 31:0
- * +16: MTRR mask 0 63:32
- * +20: MTRR base 1 31:0
- * +24: MTRR base 1 63:32
- * +28: MTRR mask 1 31:0
- * +32: MTRR mask 1 63:32
- * ...
- */
-asmlinkage void *romstage_main(unsigned long bist);
#endif
#ifdef __SMM__