1 files changed, 3 insertions, 54 deletions

diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index 722cc0102e..7baa2a81ec 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -14,7 +14,7 @@
  */
 
 #include <stdint.h>
-#include <cpu/x86/cache.h>
+#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
@@ -23,41 +23,8 @@
 #include <cpu/intel/microcode/microcode.c>
 #include "haswell.h"
 
-#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)
-/* Needed for RCBA access to set Soft Reset Data register */
 #include <southbridge/intel/lynxpoint/pch.h>
-#else
-#error "CPU must be paired with Intel LynxPoint southbridge"
-#endif
-
-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
-	unsigned int type)
-
-{
-	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
-	/* FIXME: It only support 4G less range */
-	msr_t basem, maskm;
-	basem.lo = base | type;
-	basem.hi = 0;
-	wrmsr(MTRR_PHYS_BASE(reg), basem);
-	maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
-	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
-	wrmsr(MTRR_PHYS_MASK(reg), maskm);
-}
-
-static void enable_rom_caching(void)
-{
-	msr_t msr;
-
-	disable_cache();
-	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
-	enable_cache();
-
-	/* Enable Variable MTRRs */
-	msr.hi = 0x00000000;
-	msr.lo = 0x00000800;
-	wrmsr(MTRR_DEF_TYPE_MSR, msr);
-}
+#include <cpu/intel/car/bootblock.h>
 
 static void set_flex_ratio_to_tdp_nominal(void)
 {
@@ -105,26 +72,8 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	halt();
 }
 
-static void check_for_clean_reset(void)
-{
-	msr_t msr;
-	msr = rdmsr(MTRR_DEF_TYPE_MSR);
-
-	/* Use the MTRR default type MSR as a proxy for detecting INIT#.
-	 * Reset the system if any known bits are set in that MSR. That is
-	 * an indication of the CPU not being properly reset. */
-	if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) {
-		outb(0x0, 0xcf9);
-		outb(0x6, 0xcf9);
-		halt();
-	}
-}
-
-static void bootblock_cpu_init(void)
+void bootblock_early_cpu_init(void)
 {
 	/* Set flex ratio and reset if needed */
 	set_flex_ratio_to_tdp_nominal();
-	check_for_clean_reset();
-	enable_rom_caching();
-	intel_update_microcode_from_cbfs();
 }