diff options
Diffstat (limited to 'src/cpu/intel/fsp_model_206ax/Kconfig')
| -rw-r--r-- | src/cpu/intel/fsp_model_206ax/Kconfig | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig new file mode 100644 index 0000000000..606000e4be --- /dev/null +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -0,0 +1,62 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + + +config CPU_INTEL_FSP_MODEL_206AX + bool + +config CPU_INTEL_FSP_MODEL_306AX + bool + +if CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX + +config CPU_SPECIFIC_OPTIONS + def_bool y + select PLATFORM_USES_FSP1_0 + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select SMP + select SSE2 + select UDELAY_LAPIC + select SMM_TSEG + select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN + select PARALLEL_CPU_INIT + select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER + +config BOOTBLOCK_CPU_INIT + string + default "cpu/intel/fsp_model_206ax/bootblock.c" + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + +config CPU_MICROCODE_CBFS_LOC + hex + depends on SUPPORT_CPU_UCODE_IN_CBFS + default 0xfff70000 + +endif |